SBASAH6A March   2022  – October 2022 ADS117L11

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements (1.65 V ≤ IOVDD ≤ 2 V)
    7. 6.7  Switching Characteristics (1.65 V ≤ IOVDD ≤ 2 V)
    8. 6.8  Timing Requirements (2 V < IOVDD ≤ 5.5 V)
    9. 6.9  Switching Characteristics (2 V < IOVDD ≤ 5.5 V)
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1  Offset Error Measurement
    2. 7.2  Offset Drift Measurement
    3. 7.3  Gain Error Measurement
    4. 7.4  Gain Drift Measurement
    5. 7.5  NMRR Measurement
    6. 7.6  CMRR Measurement
    7. 7.7  PSRR Measurement
    8. 7.8  INL Error Measurement
    9. 7.9  THD Measurement
    10. 7.10 SFDR Measurement
    11. 7.11 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input (AINP, AINN)
        1. 8.3.1.1 Input Range
      2. 8.3.2 Reference Voltage (REFP, REFN)
        1. 8.3.2.1 Reference Voltage Range
      3. 8.3.3 Clock Operation
        1. 8.3.3.1 Internal Oscillator
        2. 8.3.3.2 External Clock
      4. 8.3.4 Modulator
      5. 8.3.5 Digital Filter
        1. 8.3.5.1 Wideband Filter
        2. 8.3.5.2 Low-Latency Filter (Sinc)
          1. 8.3.5.2.1 Sinc4 Filter
          2. 8.3.5.2.2 Sinc4 + Sinc1 Filter
          3. 8.3.5.2.3 Sinc3 Filter
          4. 8.3.5.2.4 Sinc3 + Sinc1 Filter
      6. 8.3.6 Power Supplies
        1. 8.3.6.1 AVDD1 and AVSS
        2. 8.3.6.2 AVDD2
        3. 8.3.6.3 IOVDD
        4. 8.3.6.4 Power-On Reset (POR)
        5. 8.3.6.5 CAPA and CAPD
      7. 8.3.7 VCM Output Voltage
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Scalable Speed Modes
      2. 8.4.2 Idle Mode
      3. 8.4.3 Standby Mode
      4. 8.4.4 Power-Down Mode
      5. 8.4.5 Reset
        1. 8.4.5.1 RESET Pin
        2. 8.4.5.2 Reset by SPI Register Write
        3. 8.4.5.3 Reset by SPI Input Pattern
      6. 8.4.6 Synchronization
        1. 8.4.6.1 Synchronized Control Mode
        2. 8.4.6.2 Start/Stop Control Mode
        3. 8.4.6.3 One-Shot Control Mode
      7. 8.4.7 Conversion-Start Delay Time
      8. 8.4.8 Calibration
        1. 8.4.8.1 OFFSET2, OFFSET1, OFFSET0 Calibration Registers (Addresses 9h, Ah, Bh)
        2. 8.4.8.2 GAIN2, GAIN1, GAIN0 Calibration Registers (Addresses 0Ch, 0Dh, 0Eh)
        3. 8.4.8.3 Calibration Procedure
    5. 8.5 Programming
      1. 8.5.1 Serial Interface (SPI)
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Serial Data Input (SDI)
        4. 8.5.1.4 Serial Data Output/Data Ready (SDO/DRDY)
      2. 8.5.2 SPI Frame
      3. 8.5.3 SPI CRC
      4. 8.5.4 Register Map CRC
      5. 8.5.5 Full-Duplex Operation
      6. 8.5.6 Device Commands
        1. 8.5.6.1 No-Operation
        2. 8.5.6.2 Read Register Command
        3. 8.5.6.3 Write Register Command
      7. 8.5.7 Read Conversion Data
        1. 8.5.7.1 Conversion Data
        2. 8.5.7.2 Data Ready
          1. 8.5.7.2.1 DRDY
          2. 8.5.7.2.2 SDO/DRDY
          3. 8.5.7.2.3 DRDY Bit
          4. 8.5.7.2.4 Clock Counting
        3. 8.5.7.3 STATUS Header
      8. 8.5.8 Daisy-Chain Operation
      9. 8.5.9 3-Wire SPI Mode
        1. 8.5.9.1 3-Wire SPI Mode Frame Reset
    6. 8.6 Registers
      1. 8.6.1  DEV_ID Register (Address = 0h) [reset = 01h]
      2. 8.6.2  REV_ID Register (Address = 1h) [reset = xxh]
      3. 8.6.3  STATUS Register (Address = 2h) [reset = x1100xxxb]
      4. 8.6.4  CONTROL Register (Address = 3h) [reset = 00h]
      5. 8.6.5  MUX Register (Address = 4h) [reset = 00h]
      6. 8.6.6  CONFIG1 Register (Address = 5h) [reset = 00h]
      7. 8.6.7  CONFIG2 Register (Address = 6h) [reset = 00h]
      8. 8.6.8  CONFIG3 Register (Address = 7h) [reset = 00h]
      9. 8.6.9  CONFIG4 Register (Address = 8h) [reset = 08h]
      10. 8.6.10 OFFSET2, OFFSET1, OFFSET0 Registers (Addresses = 9h, Ah, Bh) [reset = 00h, 00h, 00h]
      11. 8.6.11 GAIN2, GAIN1, GAIN0 Registers (Addresses = Ch, Dh, Eh) [reset = 40h, 00h, 00h]
      12. 8.6.12 CRC Register (Address = Fh) [reset = 00h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Antialias Filter
      3. 9.1.3 Reference Voltage
      4. 9.1.4 Simultaneous-Sampling Systems
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.11 Noise Performance

The ADC provides two operating speed modes (high speed and low speed) that allow trade-offs between power consumption and signal bandwidth. Low-speed mode operates the modulator at 1/8th speed for decreased device power consumption and, as a result, the output data rates are reduced by 1/8th. The programmable oversampling ratio (OSR) determines the output data rate and associated signal bandwidth, and therefore also determines noise performance at the sub-LSB level.

The wideband filter provides data rates up to 400 kSPS in high-speed mode and 50 kSPS in low-speed mode. The low-latency sinc4 filter provides data rates up to 1.067 MSPS in high-speed mode and up to 133 kSPS in low-speed mode. The low-latency filter provides the options of sinc4, sinc4 + sinc1, sinc3, and sinc3 + sinc1 configurations.

For dc-signal measurements, the ADC noise can result in code flicker between adjacent code values. The probability of code flicker depends on the location of the signal input relative to the next code transition and the amplitude of the ADC noise combined with noise present within the signal. The ADC peak-to-peak noise value is typically 6.6 × the RMS noise value. Code flicker results when the amplitude of noise is large enough to trigger a code transition.

The quantization error of any ADC is ±0.5 LSB. When an ac signal is applied, the quantization error becomes a quantization noise. Figure 7-1 shows the quantization error converting to noise (LSB error plot) as the signal changes. For non-coherent sampling, this quantization noise is approximated as white noise, spread evenly across the frequency band. For any N-bit ADC, the signal-to-quantization noise ratio (SQNR) is as follows: SQNR (dB) = 6.02 × N + 1.76. For a 16-bit ADC, the SQNR is 98.1 dB.

The SNR of an ADC is determined by the sum of the device thermal noise and the device quantization noise. For most data rates of the ADS117L11, the quantization noise is larger than the thermal noise, therefore the SNR is equal to SQNR.

 

Figure 7-1 Quantization Noise of AC Signal Input

Table 7-1 through Table 7-5 summarize the noise and SNR performance and signal bandwidth of the digital filter modes. Noise and SNR performance is specified with the 1x input range and a 4.096-V reference voltage. SNR performance when operating with a 2.5-V reference voltage (1x or 2x input range) is approximately –1 dB lower at OSR = 32, increasing to the same SNR performance at OSR = 128 and above.

Table 7-1 Wideband Filter Performance (VREF = 4.096 V, 1x Input Range)
OSR DATA RATE (kSPS) –0.1-dB FREQUENCY (kHz) NOISE (µVRMS) SNR (dB)
HIGH-SPEED MODE (fCLK = 25.6 MHz)
32 400 165.000 10.6 97.3
64 200 82.500 7.47 97.5
128 100 41.250 5.20 97.8
256 50 20.625 3.66 98.0
512 25 10.312 2.58 98.0
1024 12.5 5.156 1.83 98.0
2048 6.25 2.578 1.29 98.0
4096 3.125 1.289 0.92 98.0
LOW-SPEED MODE (fCLK = 3.2 MHz)
32 50 20.625 10.6 97.3
64 25 10.312 7.47 97.5
128 12.5 5.156 5.20 97.8
256 6.25 2.578 3.66 98.0
512 3.125 1.289 2.58 98.0
1024 1.5625 0.645 1.83 98.0
2048 0.78125 0.322 1.29 98.0
4096 0.390625 0.161 0.92 98.0
Table 7-2 Sinc4 Filter Performance (VREF = 4.096 V, 1x Input Range)
OSR DATA RATE (kSPS) –3-dB FREQUENCY (kHz) NOISE (μVRMS) SNR (dB)
HIGH-SPEED MODE (fCLK = 25.6 MHz)
12 1066.666 242.666 76.3 90.5
16 800 182.000 27.3 96.0
24 533.333 121.333 10.4 97.5
32 400 91.000 7.96 97.7
64 200 45.500 5.57 98.0
128 100 22.750 3.90 98.0
256 50 11.375 2.80 98.0
512 25 5.687 1.98 98.0
1024 12.5 2.844 1.40 98.0
2048 6.25 1.422 0.99 98.0
4096 3.125 0.711 0.70 98.0
LOW-SPEED MODE (fCLK = 3.2 MHz)
12 133.333 30.333 76.3 90.5
16 100 22.750 27.3 96.0
24 66.666 15.166 10.4 97.5
32 50 11.375 7.96 97.7
64 25 5.687 5.57 98.0
128 12.5 2.844 3.90 98.0
256 6.25 1.422 2.80 98.0
512 3.125 0.711 1.98 98.0
1024 1.5625 0.355 1.40 98.0
2048 0.78125 0.177 0.99 98.0
4096 0.390625 0.089 0.70 98.0
Table 7-3 Sinc4 + Sinc1 Filter Performance (VREF = 4.096 V, 1x Input Range)
SINC4 OSR SINC1 OSR DATA RATE (kSPS) –3-dB FREQUENCY (kHz) NOISE (μVRMS) SNR (dB)
HIGH-SPEED MODE (fCLK = 25.6 MHz)
32 2 200 68.35 5.63 98.0
32 4 100 40.97 3.98 98.0
32 10 40 17.47 2.81 98.0
32 20 20 8.814 1.99 98.0
32 40 10 4.420 1.41 98.0
32 100 4 1.770 0.99 98.0
32 200 2 0.885 0.70 98.0
32 400 1 0.442 0.52 98.0
32 1000 0.4 0.177 0.39 98.0
LOW-SPEED MODE (fCLK = 3.2 MHz)
32 2 25 8.544 5.63 98.0
32 4 12.5 5.121 3.98 98.0
32 10 5 2.184 2.81 98.0
32 20 2.5 1.102 1.99 98.0
32 40 1.25 0.552 1.41 98.0
32 100 0.5 0.221 0.99 98.0
32 200 0.25 0.111 0.70 98.0
32 400 0.125 0.055 0.52 98.0
32 1000 0.05 0.022 0.39 98.0
Table 7-4 Sinc3 Filter Performance (VREF = 4.096 V, 1x Input Range)
OSR DATA RATE (SPS) –3-dB FREQUENCY (Hz) NOISE (μVRMS) SNR (dB)
HIGH-SPEED MODE (fCLK = 25.6 MHz)
26667 480 126 0.29 98.0
32000 400 105 0.27 98.0
LOW-SPEED MODE (fCLK = 3.2 MHz)
26667 60 16 0.29 98.0
32000 50 13 0.27 98.0
Table 7-5 Sinc3 + Sinc1 Filter Performance (VREF = 4.096 V, 1x Input Range)
SINC3 OSR SINC1 OSR DATA RATE (SPS) –3-dB FREQUENCY (Hz) NOISE (μVRMS) SNR (dB)
HIGH-SPEED MODE (fCLK = 25.6 MHz)
32000 3 133.3 54 0.19 98.0
32000 5 80 34 0.15 98.0
LOW-SPEED MODE (fCLK = 3.2 MHz)
32000 3 16.6 6.7 0.19 98.0
32000 5 10 4.3 0.15 98.0