SBAS301D October   2003  – February 2020 ADS1204

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Functional Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: 5.0 V
    7. 6.7 Timing Requirements: 3.0 V
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input Stage
        1. 7.3.1.1 Analog Input
        2. 7.3.1.2 Modulator
      2. 7.3.2 Digital Output
      3. 7.3.3 Equivalent Input Circuits
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Filter Usage
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Supply Sequencing
    2. 9.2 Power-Supply Decoupling
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1.1 Analog Input

The topology of the analog inputs of ADS1204 is based on fully differential switched-capacitor architecture. This input stage provides the mechanism to achieve low system noise, high common-mode rejection (100 dB), and excellent power-supply rejection.

The input impedance of the analog input is dependent on the modulator clock frequency (fCLK), which is also the sampling frequency of the modulator. Figure 28 shows the basic input structure of one channel of the ADS1204. The relationship between the input impedance of the ADS1204 and the modulator clock frequency is shown in Equation 1:

Equation 1. ADS1204 q_zin_bas301.gif

The input impedance becomes a consideration in designs where the source impedance of the input signal is high. This high impedance may cause degradation in gain, linearity, and THD. The importance of this effect depends on the desired system performance. There are two restrictions on the analog input signals, CH x+ and CH x–. If the input voltage exceeds the range (GND – 0.3 V) to (VDD + 0.3 V), the input current must be limited to 10 mA because the input protection diodes on the front end of the converter will begin to turn on. In addition, the linearity and the noise performance of the device are ensured only when the differential analog voltage resides within ±2 V (with VREF as a midpoint); however, the FSR input voltage is ±2.5 V.

ADS1204 ai_in_imp_bas301.gifFigure 28. Input Impedance of the ADS1204