SBAS301D October   2003  – February 2020 ADS1204

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Functional Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: 5.0 V
    7. 6.7 Timing Requirements: 3.0 V
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input Stage
        1. 7.3.1.1 Analog Input
        2. 7.3.1.2 Modulator
      2. 7.3.2 Digital Output
      3. 7.3.3 Equivalent Input Circuits
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Filter Usage
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Supply Sequencing
    2. 9.2 Power-Supply Decoupling
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Timing Requirements: 3.0 V(1)

over recommended operating free-air temperature range at –40°C to +105°C, AVDD = 5 V, and BVDD = 3 V (unless otherwise noted)
MIN MAX UNIT
tC1 CLKIN period 31.25 1000 ns
tW1 CLKIN high time 10 tC1 – 10 ns
tC2 CLKOUT period using internal oscillator (CLKSEL = 1) 83 125 ns
CLKOUT period using external clock (CLKSEL = 0) 2 × tC1 ns
tW2 CLKOUT high time (tC2 / 2) – 5 (tC2 / 2) + 5 ns
tD1 CLKOUT rising edge delay after CLKIN rising edge 0 10 ns
tD2 CLKOUT falling edge delay after CLKIN rising edge 0 10 ns
tD3 Data valid delay after rising edge of CLKOUT (CLKSEL = 1) (tC2 / 4) – 8 (tC2 / 4) + 8 ns
tD4 Data valid delay after rising edge of CLKOUT (CLKSEL = 0) tW1 – 3 tW1 + 7 ns
(1) Applicable for 3.0V nominal supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V. All input signals are specified with tR = tF = 5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 1.
ADS1204 tim_pmi_bas301.gifFigure 1. ADS1204 Timing Diagram