SBAS924A
July 2018 – November 2018
ADS1219
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Voltage, Current, and Temperature Monitoring Application
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
I2C Timing Requirements
6.7
I2C Switching Characteristics
6.8
Typical Characteristics
7
Parameter Measurement Information
7.1
Noise Performance
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Multiplexer
8.3.2
Rail-to-Rail Input Buffers and Programmable Gain Stage
8.3.3
Voltage Reference
8.3.4
Modulator and Internal Oscillator
8.3.5
Digital Filter
8.3.6
Conversion Times
8.3.7
Offset Calibration
8.4
Device Functional Modes
8.4.1
Power-Up and Reset
8.4.1.1
Power-On Reset
8.4.1.2
RESET Pin
8.4.1.3
Reset by Command
8.4.2
Conversion Modes
8.4.2.1
Single-Shot Conversion Mode
8.4.2.2
Continuous Conversion Mode
8.4.3
Power-Down Mode
8.5
Programming
8.5.1
I2C Interface
8.5.1.1
I2C Address
8.5.1.2
Serial Clock (SCL) and Serial Data (SDA)
8.5.1.3
Data Ready (DRDY)
8.5.1.4
Interface Speed
8.5.1.5
Data Transfer Protocol
8.5.1.6
I2C General Call (Software Reset)
8.5.1.7
Timeout
8.5.2
Data Format
8.5.3
Commands
8.5.3.1
Command Latching
8.5.3.2
RESET (0000 011x)
8.5.3.3
START/SYNC (0000 100x)
8.5.3.4
POWERDOWN (0000 001x)
8.5.3.5
RDATA (0001 xxxx)
8.5.3.6
RREG (0010 0rxx)
8.5.3.7
WREG (0100 00xx dddd dddd)
8.5.4
Reading Data and Monitoring for New Conversion Results
8.6
Register Map
8.6.1
Configuration and Status Registers
8.6.2
Register Descriptions
8.6.2.1
Configuration Register (address = 0h) [reset = 00h]
Table 10.
Configuration Register Field Descriptions
8.6.2.2
Status Register (address = 1h) [reset = 00h]
Table 11.
Status Register Field Descriptions
9
Application and Implementation
9.1
Application Information
9.1.1
Interface Connections
9.1.2
Connecting Multiple Devices on the Same I2C Bus
9.1.3
Unused Inputs and Outputs
9.1.4
Analog Input Filtering
9.1.5
External Reference and Ratiometric Measurements
9.1.6
Establishing Proper Limits on the Absolute Input Voltage
9.1.7
Pseudo Code Example
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Voltage Monitoring
9.2.2.2
High-Side Current Measurement
9.2.2.3
Thermistor Measurement
9.2.2.4
Register Settings
9.2.3
Application Curve
10
Power Supply Recommendations
10.1
Power-Supply Sequencing
10.2
Power-Supply Decoupling
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Third-Party Products Disclaimer
12.2
Documentation Support
12.2.1
Related Documentation
12.3
Receiving Notification of Documentation Updates
12.4
Community Resources
12.5
Trademarks
12.6
Electrostatic Discharge Caution
12.7
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RTE|16
MPQF149D
PW|16
MPDS361A
Thermal pad, mechanical data (Package|Pins)
RTE|16
QFND298F
Orderable Information
sbas924a_oa
sbas924a_pm
6.7
I
2
C Switching Characteristics
over operating ambient temperature range, DVDD = 2.3 V to 5.5 V, bus capacitance = 10 pF to 400 pF, and pullup resistor = 1 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
w(DRH)
Pulse duration,
DRDY
high
(1)
2
t
MOD
t
p(RDDR)
Propagation delay time, RDATA command latched to
DRDY
rising edge
2
t
MOD
(1)
t
MOD
= 1 / f
MOD
. Modulator frequency f
MOD
= 256 kHz.
Figure 1.
I
2
C Timing Requirements
Figure 2.
RESET
Pin Timing Requirements
Figure 3.
DRDY
Pin Timing Requirements and Switching Characteristics