SBAS350G June   2005  – January 2021 ADS1232 , ADS1234

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Inputs (AINPX, AINNX)
      2. 8.3.2  Temperature Sensor (ADS1232 Only)
      3. 8.3.3  Low-Noise PGA
        1. 8.3.3.1 PGA Bypass Capacitor
      4. 8.3.4  Voltage Reference Inputs (REFP, REFN)
      5. 8.3.5  Clock Sources
      6. 8.3.6  Digital Filter Frequency Response
      7. 8.3.7  Settling Time
      8. 8.3.8  Data Rate
      9. 8.3.9  Data Format
      10. 8.3.10 Data Ready and Data Output (DRDY/DOUT)
      11. 8.3.11 Serial Clock Input (SCLK)
      12. 8.3.12 Data Retrieval
    4. 8.4 Device Functional Modes
      1. 8.4.1 Offset Calibration Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Standby Mode With Offset-Calibration
      4. 8.4.4 Power-Down Mode
      5. 8.4.5 Power-Up Sequence
      6. 8.4.6 Summary of Serial Interface Waveforms
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.6 Digital Filter Frequency Response

The ADS123x use a sinc4 digital filter with the frequency response (fCLK = 4.9152 MHz) shown in Figure 8-5. The frequency response repeats at multiples of the modulator sampling frequency of 76.8 kHz. The overall response is that of a low-pass filter with a –3-dB cutoff frequency of 2.4 Hz with the SPEED pin tied low (10-SPS data rate) and 19 Hz with the SPEED pin tied high (80-SPS data rate).

GUID-4BEA0CA3-6F12-42C2-8A03-6FAA5627FE51-low.gifFigure 8-5 Digital Filter Frequency Response

To better demonstrate the response at lower frequencies, Figure 8-6(a) illustrates the response out to 100 Hz, when the data rate = 10 SPS. Notice that signals at multiples of 10 Hz are rejected, and therefore, simultaneous rejection of 50 Hz and 60 Hz interference is achieved.

The benefit of using a sinc4 filter is that every frequency notch has four zeros at the same location. This response, combined with the low-drift internal oscillator, provides an excellent normal-mode rejection of line-cycle interference.

Figure 8-6(b) shows the plot enlarged for both 50-Hz and 60-Hz notches with the SPEED pin tied low (10-SPS data rate). With only a ±3% variation of the internal oscillator, over 100 dB of normal-mode rejection is achieved.

GUID-9EB02A9B-4D86-4891-86F6-EF3E87AEED6B-low.gif Figure 8-6 Digital Filter Frequency Response to 100 Hz

The ADS123x data rate and frequency response scale directly with clock frequency. For example, if fCLK increases from 4.9152 MHz to 6.144 MHz when the SPEED pin is tied high, the data rate increases from 80 SPS to 100 SPS, while filter notches also increase from 80 Hz to 100 Hz. Frequency scaling is only possible when the external clock source is applied.