SBAS350G June   2005  – January 2021 ADS1232 , ADS1234

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Inputs (AINPX, AINNX)
      2. 8.3.2  Temperature Sensor (ADS1232 Only)
      3. 8.3.3  Low-Noise PGA
        1. 8.3.3.1 PGA Bypass Capacitor
      4. 8.3.4  Voltage Reference Inputs (REFP, REFN)
      5. 8.3.5  Clock Sources
      6. 8.3.6  Digital Filter Frequency Response
      7. 8.3.7  Settling Time
      8. 8.3.8  Data Rate
      9. 8.3.9  Data Format
      10. 8.3.10 Data Ready and Data Output (DRDY/DOUT)
      11. 8.3.11 Serial Clock Input (SCLK)
      12. 8.3.12 Data Retrieval
    4. 8.4 Device Functional Modes
      1. 8.4.1 Offset Calibration Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Standby Mode With Offset-Calibration
      4. 8.4.4 Power-Down Mode
      5. 8.4.5 Power-Up Sequence
      6. 8.4.6 Summary of Serial Interface Waveforms
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.7 Settling Time

After changing the input multiplexer, the first data are fully settled. In both ADS123x devices, the digital filter is allowed to settle after toggling either the A1 or A0 pin. Toggling any of these digital pins holds the DRDY/DOUT line high until the digital filter is fully settled. For example, if A0 changes from low to high, selecting a different input channel, DRDY/DOUT immediately goes high, and DRDY/DOUT goes low when fully settled data are ready for retrieval. There is no need to discard any data. Figure 8-7 shows the timing of the DRDY/DOUT line as the input multiplexer changes.

In certain instances, large or abrupt input changes require four data cycles to settle. One example of such a change is an external multiplexer in front of the ADS123x, which can cause large changes in input voltage simply by switching input channels. Another example is toggling the TEMP pin, which switches the internal AINP, AINN signals to connect to either the external AINPx, AINNx pins or to the TEMP diode (see Figure 8-1).

To acquire fully settled data after an input step change, five readings are required. Five readings are required because if the change in input occurs in the middle of the first conversion, four additional full conversions of the fully settled input are required to get fully settled data. Discard the first four readings because they contain only partially settled data. Figure 8-8 illustrates the settling time for the ADS123x in continuous conversion mode.

GUID-A85DE947-B897-4495-B224-BFEBB72BEADB-low.gifFigure 8-7 Example of Settling Time After Changing the Input Multiplexer
Table 8-5 Timing Requirements for Figure 8-7
PARAMETER(1) MIN MAX UNIT
tS Setup time for changing the A1 or A0 pins 40 50 μs
t1 Settling time (DRDY/DOUT held high) SPEED = 1 51 51 ms
SPEED = 0 401 401 ms
(1) Values given for fCLK = 4.9152 MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an internal oscillator is used.
GUID-B3AC4EF7-CEE0-425B-9EBB-A8E674BF35F9-low.gifFigure 8-8 Settling Time in Continuous Conversion Mode