Figure 9-1 shows a circuit diagram of the ADS1232 as part of a weigh scale system. In this setup, the ADS1232 is configured to channel 1 input, gain = 128, and 10 SPS data rate. Gain = 128 is selected by tying the GAIN[1:0] pins to logic high (3 V in this example). Input channel 1 and data rate = 10 SPS are selected by tying input channel select pins A0 and TEMP to ground, and by tying the data rate select pin SPEED to ground. The unused channel 2 inputs are tied to ground.

The internal oscillator is selected by grounding the CLKIN/XTAL1 pin. The other clock options are 1) 4.9152-MHz crystal across the CLKIN/XTAL1 and XTAL2 pins, or 2) apply a clock to the CLKIN/XTAL1 pin (pin XTAL2 unconnected). The PWDN pin of the ADC is routed to the controller because this pin must be toggled after the ADC is powered. The bridge excitation voltage is connected to the ADC reference input pins (REFP, REFN). Not shown in Figure 9-1 are R-C input filters for the signal and reference inputs. If these filters are used, match the filter time constants to maintain cancellation of noise common to both signal and reference inputs.

Figure 9-1 Weigh-Scale Application