SBAS350G June   2005  – January 2021 ADS1232 , ADS1234

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Inputs (AINPX, AINNX)
      2. 8.3.2  Temperature Sensor (ADS1232 Only)
      3. 8.3.3  Low-Noise PGA
        1. 8.3.3.1 PGA Bypass Capacitor
      4. 8.3.4  Voltage Reference Inputs (REFP, REFN)
      5. 8.3.5  Clock Sources
      6. 8.3.6  Digital Filter Frequency Response
      7. 8.3.7  Settling Time
      8. 8.3.8  Data Rate
      9. 8.3.9  Data Format
      10. 8.3.10 Data Ready and Data Output (DRDY/DOUT)
      11. 8.3.11 Serial Clock Input (SCLK)
      12. 8.3.12 Data Retrieval
    4. 8.4 Device Functional Modes
      1. 8.4.1 Offset Calibration Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Standby Mode With Offset-Calibration
      4. 8.4.4 Power-Down Mode
      5. 8.4.5 Power-Up Sequence
      6. 8.4.6 Summary of Serial Interface Waveforms
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-97E679A5-F645-4F34-B645-A089B45A285B-low.svgFigure 5-1 ADS1232 PW Package,24-Pin TSSOP,Top View
GUID-87B465BE-16AC-481D-BB16-E6D3B948D07E-low.svgFigure 5-2 ADS1234 PW Package,28-Pin TSSOP,Top View
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME ADS1232 ADS1234
A0 8 8 Digital input Input MUX select pins. See Table 8-1 and Table 8-2 for more information.
A1 — 7 Digital input Input MUX select pins. See Table 8-1 and Table 8-2 for more information.
AGND 17 21 Analog Analog ground
AINN1 12 12 Analog input Negative analog input channel 1
AINN2 13 17 Analog input Negative analog input channel 2
AINN3 — 14 Analog input Negative analog input channel 3
AINN4 — 15 Analog input Negative analog input channel 4
AINP1 11 11 Analog input Positive analog input channel 1
AINP2 14 18 Analog input Positive analog input channel 2
AINP3 — 13 Analog input Positive analog input channel 3
AINP4 — 16 Analog input Positive analog input channel 4
AVDD 18 22 Analog Analog power supply: 2.7 V to 5.3 V
CAP 9, 10 9, 10 Analog PGA bypass, connect a 0.1-µF capacitor to pins 9 and 10
CLKIN/XTAL1 3 3 Digital input External crystal connection 1, or external clock input, or tie low to activate internal oscillator. See the Section 8.3.5 section for more information.
DGND 2, 5, 6 2, 5, 6 Digital Digital ground
DRDY/DOUT 24 28 Digital output Dual-purpose output:
Data ready indicates valid data by going low.
Data output outputs data, MSB first, on the first rising edge of SCLK.
DVDD 1 1 Digital Digital power supply: 2.7 V to 5.3 V
GAIN0 19 23 Digital input Gain select pins. See the Section 8.3.3 section for more information.
GAIN1 20 24 Digital input Gain select pins. See the Low-Noise PGA section for more information.
REFN 15 19 Analog input Negative reference input
REFP 16 20 Analog input Positive reference input
PDWN 22 26 Digital input Power-down: hold this pin low to power down and reset the ADC. Toggle the pin at device power-up. See the Section 8.4.5 section for more information.
SCLK 23 27 Digital input Serial clock: clock out data on the rising edge. Also used to initiate offset calibration and standby modes. See the Section 8.4.1 and Section 8.4.3 sections for more information.
SPEED 21 25 Digital input Data rate select. See the Section 8.3.8 section for more information.
TEMP 7 — Digital input Temperature sensor select. See Table 8-1 for more information.
XTAL2 4 4 Digital External crystal connection 2