Refer to the PDF data sheet for device specific package drawings
The ADS1235 is a precision, 7200-SPS, delta-sigma (ΔΣ) analog-to-digital converter (ADC) with an integrated programmable gain amplifier (PGA). This device also includes diagnostic features such as PGA overrange and reference monitors. The ADC provides high-accuracy, zero-drift conversion data for high-precision equipment, including weigh scales, strain gauges, and resistive pressure sensors.
The ADC has signal and reference multiplexers that support three differential signal inputs and two reference inputs. The ADC also includes a low-noise PGA that provides gains of 1, 64, and 128. The ADC also has a 24-bit ΔΣ modulator and programmable digital filter.
The high-impedance inputs (1 GΩ) of the PGA reduce measurement error that is caused by sensor loading.
The ADC supports ac-bridge excitation to remove the drift errors from the sensor wiring. The ADC provides the clock control signals for the ac-excitation operation.
The flexible digital filter is programmable for single-cycle settled conversions, and provides 50-Hz and 60-Hz line cycle rejection at the same time.
The ADS1235 is available in a 5-mm × 5-mm QFN package, and is specified across the –40°C to +125°C temperature range.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADS1235 | VQFN (32) | 5.0 mm × 5.0 mm |
DATE | REVISION | NOTES |
---|---|---|
October 2018 | * | Initial release. |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | NC | — | No connection; float or connect to AVSS |
2 | CAPP | Analog output | PGA output P; connect a 4.7-nF C0G dielectric capacitor across CAPP and CAPN |
3 | CAPN | Analog output | PGA output N; connect a 4.7-nF C0G dielectric capacitor across CAPP and CAPN |
4 | AVDD | Analog | Positive analog power supply |
5 | AVSS | Analog | Negative analog power supply |
6 | NC | — | No connection - solder the pin for mechanical support, float or connect to DGND |
7 | PWDN | Digital input | Power down, active low |
8 | RESET | Digital input | Reset, active low |
9 | START | Digital input | Start conversion control, active high |
10 | CS | Digital input | Serial interface chip select, active low |
11 | SCLK | Digital Input | Serial interface shift clock |
12 | DIN | Digital Input | Serial interface data input |
13 | DRDY | Digital output | Data ready indicator, active low |
14 | DOUT/DRDY | Digital output | Dual function serial interface data output and active-low data ready indicator |
15 | BYPASS | Analog output | Internal subregulator bypass; connect a 1-µF capacitor to DGND |
16 | DGND | Digital | Digital ground |
17 | DVDD | Digital | Digital power supply |
18 | CLKIN | Digital input | 1) Internal oscillator: connect to DGND, 2) External clock: connect clock input |
19-24 | NC | — | No connection - solder the pin for mechanical support, float or connect to DGND |
25 | AIN5 | Analog input | Analog input 5 |
26 | AIN4 | Analog input | Analog input 4 |
27 | AIN3 | Analog input/output | Analog input 3, GPIO3, ACX2 |
28 | AIN2 | Analog input/output | Analog input 2, GPIO2, ACX1 |
29 | AIN1 | Analog input/output | Analog input 1, GPIO1, ACX2, Reference input 1 negative |
30 | AIN0 | Analog input/output | Analog input 0, GPIO0, ACX1, Reference input 1 positive |
31 | REFN0 | Analog input/output | Reference input 0 negative |
32 | REFP0 | Analog input/output | Reference input 0 positive |
— | Thermal Pad | — | Exposed thermal pad - solder the pad for mechanical support; connect to AVSS. |