The ADS1246, ADS1247, and ADS1248 devices are precision, 24-bit analog-to-digital converters (ADCs) that include many integrated features to reduce system cost and component count for sensor measurement applications. The devices feature a low-noise, programmable gain amplifier (PGA), a precision delta-sigma (ΔΣ) ADC with a single-cycle settling digital filter, and an internal oscillator. The ADS1247 and ADS1248 devices also provide a built-in, low-drift voltage reference, and two matched programmable excitation current sources (IDACs).
An input multiplexer supports four differential inputs for the ADS1248, two for the ADS1247, and one for the ADS1246. In addition, the multiplexer integrates sensor burn-out detection, voltage bias for thermocouples, system monitoring, and general purpose digital I/Os (ADS1247 and ADS1248). The PGA provides selectable gains up to 128 V/V. These features provide a complete front-end solution for temperature sensor measurement applications including thermocouples, thermistors, and resistance temperature detectors (RTDs) and other small signal measurements including resistive bridge sensors. The digital filter settles in a single cycle to support fast channel cycling when using the input multiplexer and provides data rates up to 2 kSPS. For data rates of 20 SPS or less, both 50-Hz and 60-Hz interference are rejected by the filter.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADS1246 | TSSOP (16) | 5.00 mm × 4.40 mm |
ADS1247 | TSSOP (20) | 6.50 mm × 4.40 mm |
ADS1248 | TSSOP (28) | 9.70 mm × 4.40 mm |
Changes from G Revision (October 2011) to H Revision
Changes from F Revision (June 2011) to G Revision
Changes from E Revision (December, 2010) to F Revision
PIN | TYPE(1) | DESCRIPTION(2) | |||
---|---|---|---|---|---|
NAME | ADS1248 (TSSOP-28) |
ADS1247 (TSSOP-20) |
ADS1246 (TSSOP-16) |
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AIN0/IEXC | 11 | 9 | — | I | Analog input 0, optional excitation current output |
AIN1/IEXC | 12 | 10 | — | I | Analog input 1, optional excitation current output |
AIN2/IEXC/GPIO2 | 17 | 11 | — | I/O | Analog input 2, optional excitation current output, or general-purpose digital input/output pin 2 |
AIN3/IEXC/GPIO3 | 18 | 12 | — | I/O | Analog input 3, optional excitation current output, or general-purpose digital input/output pin 3 |
AIN4/IEXC/GPIO4 | 13 | — | — | I/O | Analog input 4, optional excitation current output, or general-purpose digital input/output pin 4 |
AIN5/IEXC/GPIO5 | 14 | — | — | I/O | Analog input 5, optional excitation current output, or general-purpose digital input/output pin 5 |
AIN6/IEXC/GPIO6 | 15 | — | — | I/O | Analog input 6, optional excitation current output, or general-purpose digital input/output pin 6 |
AIN7/IEXC/GPIO7 | 16 | — | — | I/O | Analog input 7, optional excitation current output, or general-purpose digital input/output pin 7 |
AINN | — | — | 8 | I | Negative analog input |
AINP | — | — | 7 | I | Positive analog input |
AVDD | 22 | 14 | 10 | P | Positive analog power supply, connect a 0.1-μF capacitor to AVSS |
AVSS | 21 | 13 | 9 | P | Negative analog power supply |
CLK | 3 | 3 | 3 | I | External clock input, tie to DGND to activate the internal oscillator |
CS | 24 | 16 | 12 | I | Chip select (active low) |
DGND | 2 | 2 | 2 | G | Digital ground |
DIN | 27 | 19 | 15 | I | Serial data input |
DOUT/DRDY | 26 | 18 | 14 | O | Serial data output or data output combined with data ready |
DRDY | 25 | 17 | 13 | O | Data ready (active low) |
DVDD | 1 | 1 | 1 | P | Digital power supply, connect a 0.1-μF capacitor to DGND |
IEXC1 | 20 | — | — | O | Excitation current output 1 |
IEXC2 | 19 | — | — | O | Excitation current output 2 |
REFN | — | — | 6 | I | Negative external reference input |
REFN0/GPIO1 | 6 | 6 | — | I/O | Negative external reference input 0, or general-purpose digital input/output pin 1 |
REFN1 | 8 | — | — | I | Negative external reference input 1 |
REFP | — | — | 5 | I | Positive external reference input |
REFP0/GPIO0 | 5 | 5 | — | I/O | Positive external reference input 0, or general-purpose digital input/output pin 0 |
REFP1 | 7 | — | — | I | Positive external reference input 1 |
RESET | 4 | 4 | 4 | I | Reset (active low) |
SCLK | 28 | 20 | 16 | I | Serial clock input |
START | 23 | 15 | 11 | I | Conversion start |
VREFCOM | 10 | 8 | — | O | Negative internal reference voltage output, connect to AVSS when using a unipolar supply or to the mid-voltage of the power supply when using a bipolar supply |
VREFOUT | 9 | 7 | — | O | Positive internal reference voltage output, connect a capacitor in the range of 1-μF to 47-μF to VREFCOM |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Power-supply voltage | AVDD to AVSS | –0.3 | 5.5 | V |
AVSS to DGND | –2.8 | 0.3 | ||
DVDD to DGND | –0.3 | 5.5 | ||
Analog input voltage | AINx, REFPx, REFNx, VREFOUT, VREFCOM, IEXC1, IEXC2 | AVSS – 0.3 | AVDD + 0.3 | V |
Digital input voltage | SCLK, DIN, DOUT/DRDY, DRDY, CS, START, RESET, CLK | DGND – 0.3 | DVDD + 0.3 | V |
Input current | Continuous, any pin except power supply pins | –10 | 10 | mA |
Momentary, any pin except power supply pins | –100 | 100 | ||
Temperature | Junction, TJ | 150 | °C | |
Storage, Tstg | –60 | 150 |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V | |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
POWER SUPPLY | ||||||
Analog power supply | AVDD to AVSS | 2.7 | 5.25 | V | ||
AVSS to DGND | –2.65 | 0.1 | ||||
AVDD to DGND | 2.25 | 5.25 | ||||
Digital power supply | DVDD to DGND | 2.7 | 5.25 | V | ||
ANALOG INPUTS(2) | ||||||
VIN | Differential input voltage | V(AINP) – V(AINN)(1) | –VREF / Gain | VREF / Gain | V | |
VCM | Common-mode input voltage | (V(AINP) + V(AINN)) / 2 | See Equation 3 | V | ||
VOLTAGE REFERENCE INPUTS(3) | ||||||
VREF | Differential reference input voltage | V(REFPx) – V(REFNx) | 0.5 | (AVDD – AVSS) – 1 | V | |
V(REFNx) | Absolute negative reference voltage | AVSS – 0.1 | V(REFPx) – 0.5 | V | ||
V(REFPx) | Absolute positive reference voltage | V(REFNx) + 0.5 | AVDD + 0.1 | V | ||
EXTERNAL CLOCK INPUT(4) | ||||||
fCLK | External clock frequency | 1 | 4.5 | MHz | ||
External clock duty cycle | 25% | 75% | ||||
GENERAL-PURPOSE INPUTS/OUTPUTS (GPIO) | ||||||
GPIO input voltage | AVSS | AVDD | V | |||
DIGITAL INPUTS | ||||||
Digital input voltage | DGND | DVDD | V | |||
TEMPERATURE RANGE | ||||||
TA | Operating ambient temperature | –40 | 125 | °C | ||
Specified ambient temperature | –40 | 105 | °C |
THERMAL METRIC(1) | ADS1246 | ADS1247 | ADS1248 | UNIT | |
---|---|---|---|---|---|
PW (TSSOP) | PW (TSSOP) | PW (TSSOP) | |||
16 PINS | 20 PINS | 28 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 95.2 | 87.6 | 54.6 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 28.8 | 21.2 | 11.3 | °C/W |
RθJB | Junction-to-board thermal resistance | 41.1 | 39.9 | 13 | °C/W |
ψJT | Junction-to-top characterization parameter | 1.5 | 0.8 | 0.5 | °C/W |
ψJB | Junction-to-board characterization parameter | 40.4 | 39.2 | 12.7 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a | n/a | n/a | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ANALOG INPUTS | ||||||
Differential input current | 100 | pA | ||||
Absolute input current | See Table 8 | |||||
PGA | ||||||
PGA gain settings | 1, 2, 4, 8, 16, 32, 64, 128 | V/V | ||||
SYSTEM PERFORMANCE | ||||||
Resolution | 24 | Bits | ||||
DR | Data rate | 5, 10, 20, 40, 80, 160, 320, 640, 1000, 2000 | SPS | |||
ADC conversion time | Single-cycle settling | |||||
INL | Integral nonlinearity | Differential input, end point fit, Gain = 1, VCM = 2.5 V |
6 | 15 | ppm | |
VIO | Offset voltage (input referred) | After calibration(3) | –15 | 15 | μV | |
Offset drift | See Figure 9 to Figure 12 | |||||
Gain error | TA = 25°C, all Gains,
DR = 40 SPS, 80 SPS, or 160 SPS |
–0.02% | ±0.005% | 0.02% | ||
Gain drift | See Figure 17 to Figure 20 | |||||
Noise | See Table 1 to Table 4 | |||||
NMRR | Normal-mode rejection | See Table 10 | ||||
CMRR | Common-mode rejection | At DC, Gain = 1 | 80 | 90 | dB | |
At DC, Gain = 32 | 90 | 125 | ||||
PSRR | Power-supply rejection | AVDD / DVDD at DC, Gain = 32, DR = 80 SPS |
100 | 135 | dB | |
VOLTAGE REFERENCE INPUTS | ||||||
Reference input current | 30 | nA | ||||
INTERNAL VOLTAGE REFERENCE | ||||||
VREF | Internal reference voltage | 2.038 | 2.048 | 2.058 | V | |
Reference drift(2) | TA = 25°C to 105°C | 2 | 10 | ppm/°C | ||
TA = –40°C to 105°C | 6 | 15 | ppm/°C | |||
Output current(1) | –10 | 10 | mA | |||
Load regulation | 50 | μV/mA | ||||
Start-up time | See Table 11 | |||||
INTERNAL OSCILLATOR | ||||||
Internal oscillator frequency | 3.89 | 4.096 | 4.3 | MHz | ||
EXCITATION CURRENT SOURCES (IDACs) | ||||||
Output current settings | 50, 100, 250, 500, 750, 1000, 1500 | μA | ||||
Compliance voltage | All currents | See Figure 41 and Figure 42 | ||||
Absolute error | All currents, each IDAC | –6% | ±1% | 6% | ||
Absolute mismatch | All currents, between IDACs | ±0.15% | ||||
Temperature drift | Each IDAC | 100 | ppm/°C | |||
Temperature drift matching | Between IDACs | 10 | ppm/°C | |||
BURN-OUT CURRENT SOURCES | ||||||
Burn-out current source settings | 0.5, 2, 10 | μA | ||||
BIAS VOLTAGE | ||||||
Bias voltage | (AVDD + AVSS) / 2 | V | ||||
Bias voltage output impedance | 400 | Ω | ||||
TEMPERATURE SENSOR | ||||||
Output voltage | TA = 25°C | 118 | mV | |||
Temperature coefficient | 405 | μV/°C | ||||
GENERAL-PURPOSE INPUTS/OUTPUTS (GPIO) | ||||||
VIL | Low-level input voltage | AVSS | 0.3 × AVDD | V | ||
VIH | High-level input voltage | 0.7 × AVDD | AVDD | V | ||
VOL | Low-level output voltage | IOL = 1 mA | 0.2 × AVDD | V | ||
VOH | High-level output voltage | IOH = 1 mA | 0.8 × AVDD | V | ||
DIGITAL INPUTS/OUTPUTS (other than GPIO) | ||||||
VIL | Low-level input voltage | DGND | 0.3 × DVDD | V | ||
VIH | High-level input voltage | 0.7 × DVDD | DVDD | V | ||
VOL | Low-level output voltage | IOL = 1 mA | DGND | 0.2 × DVDD | V | |
VOH | High-level output voltage | IOH = 1 mA | 0.8 × DVDD | V | ||
Input leakage | DGND < VIN < DVDD | –10 | 10 | μA | ||
POWER SUPPLY | ||||||
IAVDD | Analog supply current | Power-down mode | 0.1 | µA | ||
Converting, AVDD = 3.3 V, DR = 20 SPS, external reference |
200 | |||||
Converting, AVDD = 5 V, DR = 20 SPS, external reference |
225 | |||||
Additional current with internal reference enabled | 180 | |||||
IDVDD | Digital supply current | Power-down mode | 0.2 | μA | ||
Normal operation, DVDD = 3.3 V, DR = 20 SPS, internal oscillator |
210 | |||||
Normal operation, DVDD = 5 V, DR = 20 SPS, internal oscillator |
230 | |||||
PD | Power dissipation | AVDD = DVDD = 5 V, DR = 20 SPS, internal oscillator, external reference |
2.3 | mW | ||
AVDD = DVDD = 3.3 V, DR = 20 SPS, internal oscillator, external reference |
1.4 |
PARAMETER | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|
SERIAL INTERFACE (SEE Figure 1 AND Figure 2) | |||||
tCSSC | Delay time, First SCLK rising edge after CS falling edge | 10 | ns | ||
tSCCS | Delay time, CS rising edge after final SCLK falling edge | 7 | tCLK(1) | ||
tCSPW | Pulse duration, CS high | 5 | tCLK | ||
tSCLK | SCLK period | 488 | ns | ||
64 | Conversions | ||||
tSPWH | Pulse duration, SCLK high | 0.25 | 0.75 | tSCLK | |
tSPWL | Pulse duration, SCLK low | 0.25 | 0.75 | tSCLK | |
tDIST | Setup time, DIN valid before SCLK falling edge | 5 | ns | ||
tDIHD | Hold time, DIN valid after SCLK falling edge | 5 | ns | ||
tSTD | Setup time, SCLK low before DRDY rising edge | 5 | tCLK | ||
tDTS | Delay time, SCLK rising edge after DRDY falling edge | 1 | tCLK | ||
MINIMUM START TIME PULSE DURATION (SEE Figure 3) | |||||
tSTART | Pulse duration, START high | 3 | tCLK | ||
RESET PULSE DURATION, SERIAL INTERFACE COMMUNICATION AFTER RESET (SEE Figure 4) | |||||
tRESET | Pulse duration, RESET low | 4 | tCLK | ||
tRHSC | Delay time, SCLK rising edge (start of serial interface communication) after RESET rising edge | 0.6(2) | ms |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tDOPD | Propagation delay time, SCLK rising edge to valid new DOUT |
DVDD ≤ 3.6 V | 50 | ns | ||
DVDD > 3.6 V | 180 | |||||
tDOHD | DOUT hold time | 0 | ns | |||
tCSDO | Propagation delay time, CS rising edge to DOUT high impedance |
10 | ns | |||
tPWH | Pulse duration, DRDY high | 3 | tCLK |