SBAS660C August   2016  – June 2017 ADS124S06 , ADS124S08

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Functional Block Diagram
  4. 4 Revision History
  5. 5 Device Family Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Multiplexer
      2. 9.3.2  Low-Noise Programmable Gain Amplifier
        1. 9.3.2.1 PGA Input-Voltage Requirements
        2. 9.3.2.2 PGA Rail Flags
        3. 9.3.2.3 Bypassing the PGA
      3. 9.3.3  Voltage Reference
        1. 9.3.3.1 Internal Reference
        2. 9.3.3.2 External Reference
        3. 9.3.3.3 Reference Buffers
      4. 9.3.4  Clock Source
      5. 9.3.5  Delta-Sigma Modulator
      6. 9.3.6  Digital Filter
        1. 9.3.6.1 Low-Latency Filter
          1. 9.3.6.1.1 Low-Latency Filter Frequency Response
          2. 9.3.6.1.2 Data Conversion Time for the Low-Latency Filter
        2. 9.3.6.2 Sinc3 Filter
          1. 9.3.6.2.1 Sinc3 Filter Frequency Response
          2. 9.3.6.2.2 Data Conversion Time for the Sinc3 Filter
        3. 9.3.6.3 Note on Conversion Time
        4. 9.3.6.4 50-Hz and 60-Hz Line Cycle Rejection
        5. 9.3.6.5 Global Chop Mode
      7. 9.3.7  Excitation Current Sources (IDACs)
      8. 9.3.8  Bias Voltage Generation
      9. 9.3.9  System Monitor
        1. 9.3.9.1 Internal Temperature Sensor
        2. 9.3.9.2 Power Supply Monitors
        3. 9.3.9.3 Burn-Out Current Sources
      10. 9.3.10 Status Register
        1. 9.3.10.1 POR Flag
        2. 9.3.10.2 RDY Flag
        3. 9.3.10.3 PGA Output Voltage Rail Monitors
        4. 9.3.10.4 Reference Monitor
      11. 9.3.11 General-Purpose Inputs and Outputs (GPIOs)
      12. 9.3.12 Low-Side Power Switch
      13. 9.3.13 Cyclic Redundancy Check (CRC)
      14. 9.3.14 Calibration
        1. 9.3.14.1 Offset Calibration
        2. 9.3.14.2 Gain Calibration
    4. 9.4 Device Functional Modes
      1. 9.4.1 Reset
        1. 9.4.1.1 Power-On Reset
        2. 9.4.1.2 RESET Pin
        3. 9.4.1.3 Reset by Command
      2. 9.4.2 Power-Down Mode
      3. 9.4.3 Standby Mode
      4. 9.4.4 Conversion Modes
        1. 9.4.4.1 Continuous Conversion Mode
        2. 9.4.4.2 Single-Shot Conversion Mode
        3. 9.4.4.3 Programmable Conversion Delay
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip Select (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Serial Data Input (DIN)
        4. 9.5.1.4 Serial Data Output and Data Ready (DOUT/DRDY)
        5. 9.5.1.5 Data Ready (DRDY)
        6. 9.5.1.6 Timeout
      2. 9.5.2 Data Format
      3. 9.5.3 Commands
        1. 9.5.3.1  NOP
        2. 9.5.3.2  WAKEUP
        3. 9.5.3.3  POWERDOWN
        4. 9.5.3.4  RESET
        5. 9.5.3.5  START
        6. 9.5.3.6  STOP
        7. 9.5.3.7  SYOCAL
        8. 9.5.3.8  SYGCAL
        9. 9.5.3.9  SFOCAL
        10. 9.5.3.10 RDATA
        11. 9.5.3.11 RREG
        12. 9.5.3.12 WREG
      4. 9.5.4 Reading Data
        1. 9.5.4.1 Read Data Direct
        2. 9.5.4.2 Read Data by RDATA Command
        3. 9.5.4.3 Sending Commands When Reading Data
      5. 9.5.5 Interfacing with Multiple Devices
    6. 9.6 Register Map
      1. 9.6.1 Configuration Registers
        1. 9.6.1.1  Device ID Register (address = 00h) [reset = xxh]
          1. Table 26. Device ID (ID) Register Field Descriptions
        2. 9.6.1.2  Device Status Register (address = 01h) [reset = 80h]
          1. Table 27. Device Status (STATUS) Register Field Descriptions
        3. 9.6.1.3  Input Multiplexer Register (address = 02h) [reset = 01h]
          1. Table 28. Input Multiplexer (INPMUX) Register Field Descriptions
        4. 9.6.1.4  Gain Setting Register (address = 03h) [reset = 00h]
          1. Table 29. Gain Setting (PGA) Register Field Descriptions
        5. 9.6.1.5  Data Rate Register (address = 04h) [reset = 14h]
          1. Table 30. Data Rate (DATARATE) Register Field Descriptions
        6. 9.6.1.6  Reference Control Register (address = 05h) [reset = 10h]
          1. Table 31. Reference Control (REF) Register Field Descriptions
        7. 9.6.1.7  Excitation Current Register 1 (address = 06h) [reset = 00h]
          1. Table 32. Excitation Current Register 1 (IDACMAG) Register Field Descriptions
        8. 9.6.1.8  Excitation Current Register 2 (address = 07h) [reset = FFh]
          1. Table 33. Excitation Current Register 2 (IDACMUX) Register Field Descriptions
        9. 9.6.1.9  Sensor Biasing Register (address = 08h) [reset = 00h]
          1. Table 34. Sensor Biasing (VBIAS) Register Field Descriptions
        10. 9.6.1.10 System Control Register (address = 09h) [reset = 10h]
          1. Table 35. System Control (SYS) Register Field Descriptions
        11. 9.6.1.11 Offset Calibration Register 1 (address = 0Ah) [reset = 00h]
          1. Table 36. Offset Calibration Register 1 (OFCAL0) Register Field Descriptions
        12. 9.6.1.12 Offset Calibration Register 2 (address = 0Bh) [reset = 00h]
          1. Table 37. Offset Calibration Register 2 (OFCAL1) Register Field Descriptions
        13. 9.6.1.13 Offset Calibration Register 3 (address = 0Ch) [reset = 00h]
          1. Table 38. Offset Calibration Register 3 (OFCAL2) Register Field Descriptions
        14. 9.6.1.14 Gain Calibration Register 1 (address = 0Dh) [reset = 00h]
          1. Table 39. Gain Calibration Register 1 (FSCAL0) Register Field Descriptions
        15. 9.6.1.15 Gain Calibration Register 2 (address = 0Eh) [reset = 00h]
          1. Table 40. Gain Calibration Register 2 (FSCAL1) Field Descriptions
        16. 9.6.1.16 Gain Calibration Register 3 (address = 0Fh) [reset = 40h]
          1. Table 41. Gain Calibration Register 3 (FSCAL2) Field Descriptions
        17. 9.6.1.17 GPIO Data Register (address = 10h) [reset = 00h]
          1. Table 42. GPIO Data (GPIODAT) Register Field Descriptions
        18. 9.6.1.18 GPIO Configuration Register (address = 11h) [reset = 00h]
          1. Table 43. GPIO Configuration (GPIOCON) Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Serial Interface Connections
      2. 10.1.2 Analog Input Filtering
      3. 10.1.3 External Reference and Ratiometric Measurements
      4. 10.1.4 Establishing a Proper Input Voltage
      5. 10.1.5 Unused Inputs and Outputs
      6. 10.1.6 Pseudo Code Example
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Register Settings
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
    2. 11.2 Power-Supply Sequencing
    3. 11.3 Power-On Reset
    4. 11.4 Power-Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Related Links
    4. 13.4 Receiving Notification of Documentation Updates
    5. 13.5 Community Resources
    6. 13.6 Trademarks
    7. 13.7 Electrostatic Discharge Caution
    8. 13.8 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
  • PBS|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.2.2 Detailed Design Procedure

The key considerations in the design of a 3-wire RTD circuit are the accuracy, the lead wire compensation, and the sensor self-heating. As the design values of Table 45 show, several values of excitation currents are available. The resolution is expressed in units of noise-free resolution (NFR). Noise-free resolution is resolution with no code flicker. The selection of excitation currents trades off resolution against sensor self-heating. In general, measurement resolution improves with increasing excitation current. Increasing the excitation current beyond 1000 µA results in no further improvement in resolution for this example circuit. The design procedure is based on a 500-µA excitation current, because this level of current results in very low sensor self-heating
(0.4 mW).

Table 45. RTD Circuit Design Parameters

IIDAC (µA)NFR (bits)PRTD (mW)VRTD
(V)		Gain
(V/V)		VREFMIN(1)
(V)		VREF(2)
(V)		RREF
(kΩ)		VAINNLIM(3)
(V)		VAINPLIM(4)
(V)		RBIAS
(kΩ)		VRTDN(5)
(V)		VRTDP(6)
(V)		VIDAC1(7)
(V)
50 16.8 0.001 0.02 32 0.64 0.70 18 0.6 4.1 7.10 0.7 0.7 1.9
100 17.8 0.004 0.04 32 1.28 1.41 14.1 0.9 3.8 5.10 1.0 1.1 2.8
250 18.8 0.025 0.10 16 1.60 1.76 7.04 1.1 3.7 2.30 1.2 1.3 3.3
500 19.1 0.100 0.20 8 1.60 1.76 3.52 1.0 3.8 1.10 1.1 1.3 3.4
750 18.9 0.225 0.30 4 1.20 1.32 1.76 0.8 4.0 0.57 0.9 1.2 2.8
1000 19.3 0.400 0.40 4 1.60 1.76 1.76 0.9 3.9 0.50 1.0 1.4 3.5
1500 19.1 0.900 0.60 2 1.20 1.32 0.88 0.6 4.2 0.23 0.7 1.3 3.0
2000 18.3 1.600 0.80 1 0.80 0.90 0.45 0.3 4.5 0.10 0.4 1.2 2.4
(1) VREFMIN is the minimum reference voltage required by the design.
(2) VREF is the design target reference voltage allowing for 10% overrange.
(3) VAINNLIM is the absolute minimum input voltage required by the ADC.
(4) VAINPLIM is the absolute maximum input voltage required by the ADC.
(5) VRTDN is the design target negative input voltage.
(6) VRTDP is the design target positive input voltage.
(7) VIDAC1 is the design target IDAC1 loop voltage.

Initially, RLEAD1 and RLEAD2 are considered to be 0 Ω. Route the IDAC1 current through the external reference resistor, RREF. IDAC1 generates the ADC reference voltage, VREF, across the reference resistor. This voltage is defined by Equation 12:

Equation 12. VREF = IIDAC1 · RREF

Route the second current (IDAC2) to the second RTD lead.

Program the IDAC value by using the IDACMAG register; however, only the IDAC1 current flows through the reference resistor and RTD. The IDAC1 current excites the RTD to produce a voltage proportional to the RTD resistance. The RTD voltage is defined by Equation 13:

Equation 13. VRTD = RRTD · IIDAC1

The ADC amplifies the RTD signal voltage (VRTD) and measures the resulting voltage against the reference voltage to produce a proportional digital output code, as shown in Equation 14 through Equation 16.

Equation 14. Code ∝ VRTD · Gain / VREF
Equation 15. Code ∝ (RRTD · IIDAC1) · Gain / (IIDAC1 · RREF)
Equation 16. Code ∝ (RRTD · Gain) / RREF

As shown in Equation 16, the RTD measurement depends on the value of the RTD, the PGA gain, and the reference resistor RREF, but not on the IDAC1 value. Therefore, the absolute accuracy and temperature drift of the excitation current does not matter.

The second excitation current (IDAC2) provides a second voltage drop across the second RTD lead resistance, RLEAD2. The second voltage drop compensates the voltage drop caused by IDAC1 and RLEAD1. The leads of a 3-wire RTD typically have the same length; therefore, the lead resistance is typically identical. Taking the lead resistance into account (RLEADx ≠ 0), the differential voltage (VIN) across ADC inputs AIN8 and AIN9 is shown in Equation 17:

Equation 17. VIN = IIDAC1 · (RRTD + RLEAD1) – IIDAC2 · RLEAD2

If RLEAD1 = RLEAD2 and IIDAC1 = IIDAC2, the expression for VIN reduces to Equation 18:

Equation 18. VIN = IIDAC1 · RRTD

In other words, the measurement error resulting from the voltage drop across the RTD lead resistance is compensated as long as the lead resistance values and the IDAC values are matched.

Using Equation 13, the value of RTD resistance (400 Ω, maximum) and the excitation current (500 µA) yields an RTD voltage of VRTD = 500 µA · 400 Ω = 0.2 V. Use the maximum gain of 8 in order to limit the corresponding loop voltage of IDAC1. Gain = 8 requires a minimum reference voltage VREFMIN = 0.2 V · 8 = 1.6 V. To provide margin for the ADC operating range, increase the target reference voltage by 10% (VREF = 1.6 V · 1.1 = 1.76 V). Calculate the value of the reference resistor, as shown in Equation 19:

Equation 19. RREF = VREF / IIDAC1 = 1.76 V / 500 µA = 3.52 kΩ

For this example application, 3.5 kΩ is chosen for RREF. For best results, use a precision reference resistor RREF with a low temperature drift (< 10 ppm/°C). Any change in RREF is reflected in the measurement as a gain error.

The next step in the design is determining the value of the RBIAS resistor, in order to level shift the RTD voltage to meet the ADC absolute input-voltage specification. The required level-shift voltage is determined by calculating the minimum absolute voltage (VAINNLIM) as shown in Equation 20:

Equation 20. AVSS + 0.15 + VRTDMAX · (Gain – 1) / 2 ≤ VAINNLIM

where

  • VRTDMAX = maximum differential RTD voltage = 0.2 V
  • Gain = 8
  • AVSS = 0 V

The result of the equation requires a minimum absolute input voltage (VRTDN) > 0.85 V. Therefore, the RTD voltage must be level shifted by a minimum of 0.85 V. To meet this requirement, a target level-shift value of 1 V is chosen to provide extra margin. Calculate the value of RBIAS as shown in Equation 21:

Equation 21. RBIAS= VAINN / (IIDAC1+ IIDAC2) = 1 V / ( 2 · 500 µA) = 1 kΩ

After the level-shift voltage is determined, verify that the positive RTD voltage (VRTDP) is less than the maximum absolute input voltage (VAINPLIM), as shown in Equation 22:

Equation 22. VAINPLIM ≤ AVDD – 0.15 – VRTDMAX · (Gain – 1) / 2

where

  • VRTDMAX = maximum differential RTD voltage = 0.2 V
  • Gain = 8
  • AVDD = 4.75 V (minimum)

Solving Equation 22 results in a required VRTDP of less than 3.9 V. Calculate the VRTDP input voltage by Equation 23:

Equation 23. VAINP = VRTDN + IIDAC1 · (RRTD + RLEAD1) = 1 V + 500 µA · (400 Ω + 10 Ω) = 1.2 V

Because 1.2 V is less than the 3.9-V maximum input voltage limit, the absolute positive and negative RTD voltages are within the ADC specified input range.

The next step in the design is to verify that the IDACs have enough voltage headroom (compliance voltage) to operate. The loop voltage of the excitation current must be less than the supply voltage minus the specified IDAC compliance voltage. Calculate the voltage drop developed across each IDAC current path to AVSS. In this circuit, IDAC1 has the largest voltage drop developed across its current path. The IDAC1 calculation is sufficient to satisfy IDAC2 because the IDAC2 voltage drop is always less than IDAC1 voltage drop. The sum of voltages in the IDAC1 loop is shown in Equation 24:

Equation 24. VIDAC1 = [(IIDAC1 + IIDAC2) · (RLEAD3 + RBIAS)] + [IIDAC1 · (RRTD + RLEAD1 + RREF)] + VD

where

  • VD = external blocking diode voltage

The equation results in a loop voltage of VIDAC1 = 3.0 V. The worst-case current source compliance voltage is: (AVDD – 0.4 V) = (4.75 V – 0.4 V) = 4.35 V. The VIDAC1 loop voltage is less than the specified current source compliance voltage (3.0 V < 4.35 V).

Many applications benefit from using an analog filter at the inputs to remove noise and interference from the signal. Filter components are placed on the ADC inputs (RF1, RF2, CDIF1, CCM1, and CCM2), as well as on the reference inputs (RF3, RF4, CDIF2, CCM3, and CCM4). The filters remove both differential and common-mode noise. The application shows a differential input noise filter formed by RF1, RF2 and CDIF1, with additional differential mode capacitance provided by the common-mode filter capacitors, CCM1 and CCM2. Calculate the differential
–3-dB cutoff frequency as shown in Equation 25:

Equation 25. fDIF = 1 / [2π · (RF1 + RF2) · (CDIF1 + CCM1|| CCM2)]

The common-mode noise filter is formed by components RF1, RF2, CCM1, and CCM2. Calculate the common-mode signal –3-dB cutoff frequency, as shown in Equation 26:

Equation 26. fCM = 1 / (2π · RF1 · CCM1) = 1 / (2π · RF2 · CCM2)

Mismatches in the common-mode filter components convert common-mode noise into differential noise. To reduce the effect of mismatch, use a differential mode filter with a corner frequency that is at least 10 times lower than the common-mode filter corner frequency. The low-frequency differential filter removes the common-mode converted noise. The filter resistors (RFx) also serve as current-limiting resistors. These resistors limit the current into the analog inputs (AINx) of the device to safe levels when an overvoltage occurs on the inputs.

Filter resistors lead to an offset voltage error due to the dc input current leakage flowing into and out of the device. Remove this voltage error by system offset calibration. Resistor values that are too large generate excess thermal noise and degrade the overall noise performance. The recommended range of the filter resistor values is 100 Ω to 10 kΩ. The properties of the capacitors are important because the capacitors are connected to the signal; use high-quality C0G ceramics or film-type capacitors.

For consistent noise performance across the full range of RTD measurements, match the corner frequencies of the input and reference filter. See the RTD Ratiometric Measurements and Filtering Using the ADS1148 and ADS1248 Application Report (SBAA201) for detailed information on matching the input and reference filter.