SBAS790C October 2018 – June 2019 ADS125H02
PRODUCTION DATA.
Table 28 shows the device register map consisting of 19 one-byte registers. Collectively, the registers are used to configure the device to the desired operating mode. Access the registers by using the RREG and WREG commands (register-read and register-write, respectively). Data are accessed one register byte at a time for each command operation. The address of the register corresponds to using either CS1 or CS2 for the register command operation. The CSx column shows the correlation of CS1 or CS2 to the register address. Changing the data of certain registers results in a restart of conversions already in progress. The Restart column lists these registers.
ADDRESS | REGISTER | DEFAULT | RESTART | CSx | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|
00h | ID | 6xh | CS1 | DEV_ID[3:0] | REV_ID1[3:0] | |||||||
01h | STATUS0 | 01h | CS1 | LOCK1 | CRC1 | 0 | STAT12 | REFALM | DRDY | CLOCK | RESET | |
02h | MODE0 | 24h | Yes | CS1 | DR[4:0] | FILTER[2:0] | ||||||
03h | MODE1 | 01h | Yes | CS1 | 0 | 0 | AUTOZERO | CONVRT | DELAY[3:0] | |||
04h | MODE2 | 00h | CS1 | GPIO_CON[3:0] | GPIO_DIR[3:0] | |||||||
05h | MODE3 | 00h | CS1 | 0 | STATENB | 0 | 0 | GPIO_DAT[3:0] | ||||
06h | REF | 05h | Yes | CS1 | 0 | 0 | 0 | REFENB | RMUXP[1:0] | RMUXN[1:0] | ||
07h | OFCAL0 | 00h | CS1 | OFC[7:0] | ||||||||
08h | OFCAL1 | 00h | CS1 | OFC[15:8] | ||||||||
09h | OFCAL2 | 00h | CS1 | OFC[23:16] | ||||||||
0Ah | FSCAL0 | 00h | CS1 | FSC[7:0] | ||||||||
0Bh | FSCAL1 | 00h | CS1 | FSC[15:8] | ||||||||
0Ch | FSCAL2 | 40h | CS1 | FSC[23:16] | ||||||||
0Dh | I_MUX | FFh | CS1 | I_MUX2[3:0] | I_MUX1[3:0] | |||||||
0Eh | I_MAG | 00h | CS1 | I_MAG2[3:0] | I_MAG1[3:0] | |||||||
0Fh | RESERVED | 00h | CS1 | 00h | ||||||||
10h | MODE4 | 50h | CS2 | 0 | MUX[2:0] | GAIN[3:0] | ||||||
11h | STATUS1 | xxh | CS2 | PGA_ONL | PGA_ONH | PGA_OPL | PGA_OPH | PGA_INL | PGA_INH | PGA_IPL | PGA_IPH | |
12h | STATUS2 | 0xh | CS2 | 0 | 0 | LOCK2 | CRC2 | REV_ID2[3:0] |
Table 29 lists the access codes for the ADS125H02 registers.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R/W | R-W | Read or write |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |