SBAS760C March 2018 – January 2019 ADS1260 , ADS1261
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The ADS1260 and ADS1261 are 5-channel and 10-channel, precision 24-bit, delta-sigma (ΔΣ) ADCs with an integrated analog front end (AFE) and voltage reference. The low-noise and low-drift architecture make the ADCs suitable for precision measurement of low signal level sensors, such as strain-gauge bridges, pressure transducers and temperature sensors.
Key features of the ADC are:
The analog inputs (AINx) connect to the input multiplexer (MUX). The ADC supports three (five) differential or five (ten) single-ended input configurations for the ADS1260 and ADS1261, respectively.
The programmable gain amplifier (PGA) follows the input multiplexer. The PGA is suitable for direct connection to low-level sensors. The gain is programmable from 1 to 128. The PGA bypass option connects the analog inputs directly to the precharge buffered modulator, extending the input voltage range to the power supplies. The PGA output connects to pins CAPP and CAPN. The ADC antialias filter is provided at the PGA output with an external capacitor.
The PGA is monitored to verify linear operation. Alarm bits in the status register set if the linear range of the PGA is exceeded.
A delta-sigma modulator measures the input voltage relative to the reference voltage to produce the 24-bit conversion result. The differential input range of the ADC is ±VREF / Gain.
The digital filter averages and decimates the modulator output data to yield the final, down-sampled conversion result. The sinc filter is programmable (sinc1 through sinc5) allowing optimization of conversion time, conversion noise and line-cycle rejection. The finite impulse response (FIR) filter mode provides single-cycle settled data with simultaneous rejection of 50-Hz and 60-Hz at data rates of 20 SPS or less.
The ADC reference is either 2.5-V internal, external or the 5-V analog power supply. The REFOUT pin provides the buffered reference voltage output. The external reference is monitored for low or missing voltage. The ADS1261 provides two voltage reference inputs, multiplexed with the analog inputs.
The ADC includes two current sources that provide excitation to resistive sensors (RTD). Additionally, the ADS1261 provides four GPIO control lines. The GPIOs are used for input and output of general-purpose logic signals, as well as providing drive signals for AC-excited bridges. The GPIOs are multiplexed to the analog inputs.
The temperature sensor and the power supply voltages are read through the multiplexer. The programmable burn-out test currents connect to the multiplexer output. The currents detect failed sensors or faults in the sensor connection. The level-shift voltage on AINCOM provides the bias for floating sensors.
The SPI-compatible serial interface is used to read the conversion data and also to configure and control the ADC. Data communication errors are detected by CRC. The serial interface consists of four signals: CS, SCLK, DIN and DOUT/DRDY. The dual function DOUT/DRDY provides data output and also the data ready signal. The ADC serial interface can be implemented with as little as three pins by tying CS low.
The ADC clock is either internal or external. The ADC detects the external clock automatically. The nominal clock frequency is 7.3728 MHz (10.24 MHz for 40-kSPS operation).
ADC conversions are controlled by the START pin or by the START command. The ADC is programmable for continuous or one-shot conversions. The DRDY or DOUT/DRDY pin provides the conversion data ready signal. When taken low, the RESET pin resets the ADC. The ADC is powered down by the PWDN pin or is powered down in software mode.
The ADC operates in either bipolar analog supply configuration (±2.5 V), or in a single 5-V supply configuration. The digital power supply range is 2.7 V to 5 V. The BYPASS pin is the internal subregulator output used for the ADC digital core.