SBASAM0A March 2024 – June 2024 ADS127L18
ADVANCE INFORMATION
SCLK is the serial clock input that shifts register data into and out of the ADC. Register output data update on the SCLK rising edge and register input data latch on the SCLK falling edge. SCLK is a Schmitt-triggered input designed to increase noise immunity. Even though SCLK is noise resistant, keep SCLK as noise-free as possible to avoid unintentional SCLK transitions. Avoid ringing and overshoot on the SCLK input. A series termination resistor at the SCLK driver often reduces ringing.