SBASAM0A March 2024 – June 2024 ADS127L18
ADVANCE INFORMATION
The frame-sync CRC is an optional byte appended to the end of conversion data. The CRC is eight bits and is calculated over each channel data and, if enabled, includes the STATUS_DP byte. The argument for the CRC calculation is 16 bits, 24 bits, or 32 bits. The number of bits reflects the mode used. For 16 bits, use 16-bit data mode. For 24 bits, use the 24-bit data mode or the STATUS_DP byte plus 16 bits of data. For 32 bits, use the STATUS_DP byte plus 24 bits of data. The CRC uses the same CRC-8_ATM polynomial as the SPI CRC. The DP_CRC_EN bit of the DP_CFG1 register enables the CRC byte.