The ADS127L14 and ADS127L18 are quad and octal, 24-bit, high-resolution, simultaneous-sampling, delta-sigma (ΔΣ) analog-to-digital converters (ADCs). The devices offer an excellent combination of dc accuracy, ac resolution, and wide signal bandwidth for synchronized, multichannel data acquisition systems. The ADCs are optimized for high resolution and wide signal bandwidths with low power consumption.

The Functional Block Diagram shows the device features. The devices consist of four or eight independent delta-sigma ADCs from which data is read through a frame-sync data port. Each ADC has programmable digital filters that provide sample rates up to 512kSPS in wideband filter mode and 1365.3kSPS in low-latency filter mode. Four selectable power-scalable speed modes allow optimization of signal bandwidth, resolution, and power consumption.

Signal and reference voltage input precharge buffers of each ADC channel reduce analog input current and sampling noise to allow the use of low bandwidth signal drivers. The VCM output is a buffered mid-supply voltage used to drive the common-mode voltage of external buffers and gain stages.

The multibit ΔΣ modulator measures the differential input signal, V_IN = (V_AINP – V_AINN), against the differential reference, V_REF = (V_REFP – V_REFN). The modulator produces low-resolution, high-frequency data. Noise shaping of the modulator shifts the quantization noise of the low-resolution data to an out-of-band frequency range where the digital filter removes this noise. The noise remaining within the pass band is low-level thermal noise. The digital filter decimates and filters the modulator data to provide high-resolution output data.

The digital filter has two filter modes: low-latency filter (typically used for dc signal measurement) and wideband filter (typically used for ac signal measurement). The low-latency filter is a variable-order sinc filter with filter options for sinc4, sinc4 + sinc1, sinc3, and sinc3 + sinc1. This filter allows optimization between noise performance, conversion latency, and signal bandwidth. The wideband filter is a multi-stage, linear phase finite impulse response (FIR) filter. This filter provides outstanding frequency response characteristics with low pass-band ripple, narrow transition-band, and high stop-band attenuation. The devices allow power-of-2 related data rates between channels.

The MODE pin selects the method of device configuration: by hardware pin settings or by the SPI serial interface.

The frame-sync data port provides the conversion data using four or eight data lanes or time division multiplex (TDM) format to reduce the number of data lanes. Daisy-chain multiple devices by routing the DOUTx pins to the DINx pins of the chained devices.

The device supports external clock operation for ac or dc signal applications and internal oscillator operation for dc signal applications. The START pin simultaneously synchronizes the ADC channels. The RESET pin resets the ADC.

Cyclic redundancy check (CRC) error detection is available for the frame-sync port and the SPI configuration port. The register map CRC operates in the background to detect unintended changes to the register values after the initial values are uploaded to the device. The open-drain ERROR output pin asserts low when an ADC error is detected.

Eight general-purpose input/output (GPIO) pins are available. Two GPIOs are standalone pins and the remaining six GPIO pins are multiplexed with the frame-sync DINx and DOUTx pins.

The AVDD1 supply voltage powers the precharge buffers and the input sampling switches. AVDD2 powers the modulators through an internal voltage regulator. The IOVDD supply voltage is the digital I/O voltage and also powers the digital cores through a second voltage regulator. The internal regulators reduce overall power consumption and maintain consistent levels of device performance under varying power supply conditions.