SBASAM0A March 2024 – June 2024 ADS127L18
ADVANCE INFORMATION
A DOUT offset timing adjustment is provided to help meet external timing requirements of the frame-sync port. The offset timing delays or advances the DOUT signals relative to the FSYNC and DCLK signals. The total offset range is ±6ns, relative to the nominal DOUT timing in the Switching Characteristics. Figure 7-40 shows the offset timing operation. The timing between the FSYNC and DCLK signals is fixed. The signed-magnitude DOUT_DLY[4:0] bits of the DP_CFG2 register control the DOUT offset timing.