SBASAM0B March   2024  – November 2024 ADS127L18

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Clock Dividers
        2. 7.3.3.2 Internal Oscillator
        3. 7.3.3.3 External Clock
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 VCM Output Voltage
      6. 7.3.6 GPIO
      7. 7.3.7 Modulator
      8. 7.3.8 Digital Filter
        1. 7.3.8.1 Wideband Filter
        2. 7.3.8.2 Low-Latency Filter (Sinc)
          1. 7.3.8.2.1 Sinc4 Filter
          2. 7.3.8.2.2 Sinc4 + Sinc1 Cascade Filter
          3. 7.3.8.2.3 Sinc3 Filter
          4. 7.3.8.2.4 Sinc3 + Sinc1 Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1  Reset
        1. 7.4.1.1 RESET Pin
        2. 7.4.1.2 Reset by SPI Register
        3. 7.4.1.3 Reset by SPI Input Pattern
      2. 7.4.2  Idle and Standby Modes
      3. 7.4.3  Power-Down
      4. 7.4.4  Speed Modes
      5. 7.4.5  Synchronization
        1. 7.4.5.1 Synchronized Control Mode
        2. 7.4.5.2 Start/Stop Control Mode
      6. 7.4.6  Conversion-Start Delay Time
      7. 7.4.7  Calibration
        1. 7.4.7.1 Offset Calibration Registers
        2. 7.4.7.2 Gain Calibration Registers
        3. 7.4.7.3 Calibration Procedure
      8. 7.4.8  Data Averaging
      9. 7.4.9  Diagnostics
        1. 7.4.9.1 ERROR Pin and ERR_FLAG Bit
        2. 7.4.9.2 SPI CRC
        3. 7.4.9.3 Register Map CRC
        4. 7.4.9.4 ADC Error
        5. 7.4.9.5 SPI Address Range
        6. 7.4.9.6 SCLK Counter
        7. 7.4.9.7 Clock Counter
        8. 7.4.9.8 Frame-Sync CRC
        9. 7.4.9.9 Self Test
      10. 7.4.10 Frame-Sync Data Port
        1. 7.4.10.1  Data Packet
        2. 7.4.10.2  Data Format
        3. 7.4.10.3  STATUS_DP Header Byte
        4. 7.4.10.4  FSYNC Pin
        5. 7.4.10.5  DCLK Pin
        6. 7.4.10.6  DOUTx Pins
        7. 7.4.10.7  DINx Pins
        8. 7.4.10.8  Time Division Multiplexing
        9. 7.4.10.9  Daisy Chain
        10. 7.4.10.10 DOUTx Timing
    5. 7.5 Programming
      1. 7.5.1 Hardware Programming
      2. 7.5.2 SPI Programming
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output (SDO)
      3. 7.5.3 SPI Frame
      4. 7.5.4 Commands
        1. 7.5.4.1 Write Register Command
        2. 7.5.4.2 Read Register Command
      5. 7.5.5 SPI Daisy-Chain
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Antialias Filter
      3. 9.1.3 Reference Voltage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 AVDD1 and AVSS
      2. 9.3.2 AVDD2
      3. 9.3.3 IOVDD
      4. 9.3.4 CAPA and CAPD
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.8.1 Wideband Filter

The wideband filter is a multistage FIR design featuring linear phase response, flat pass-band amplitude, narrow transition band, and high stop-band attenuation. Because of these characteristics, it is the recommended filter for measuring ac signals. The ADC provides eight programmable OSR values and four speed modes, offering a range of data rate, bandwidth and resolution options.

Figure 7-12 through Figure 7-16 illustrate the frequency response of the wideband filter. Figure 7-12 shows details of the pass-band ripple. Figure 7-13 shows the frequency response at the transition band.

ADS127L14 ADS127L18 Wideband Filter Pass-Band Ripple
 
Figure 7-12 Wideband Filter Pass-Band Ripple
ADS127L14 ADS127L18 Wideband Filter Transition Band
 
Figure 7-13 Wideband Filter Transition Band

Figure 7-14 shows the frequency response to fDATA for OSR ≥ 64. The stop band begins at fDATA / 2 to prevent aliasing at the Nyquist frequency. Figure 7-15 shows the stop-band attenuation to fMOD for OSR = 32. In the stop-band region, out-of-band input frequencies mix with multiples of the fMOD / 32 chop frequency. This process creates a pattern of stop-band response peaks that exceed the attenuation provided by the digital filter. The width of the response peaks is twice the filter bandwidth. Stop-band attenuation is improved when used in conjunction with an antialias filter at the ADC input.

ADS127L14 ADS127L18 Wideband Filter Frequency Response
OSR ≥ 64
Figure 7-14 Wideband Filter Frequency Response
ADS127L14 ADS127L18 Wideband Filter Stop-Band
OSR = 32
Figure 7-15 Wideband Filter Stop-Band

Figure 7-16 shows the filter response centered at fMOD, where the filter response repeats. If not removed by an antialiasing filter, input frequencies at fMOD appear as aliased frequencies in the pass band. Aliasing also occurs by input frequencies occurring at multiples of fMOD. These frequency bands are defined by:

Equation 18. Alias frequency bands: (N · fMOD) ± fBW

where:

  • N = 1, 2, 3, and so on
  • fMOD = Modulator sampling frequency
  • fBW = Filter bandwidth

ADS127L14 ADS127L18 Wideband Filter Frequency Response Centered at fMOD
 
Figure 7-16 Wideband Filter Frequency Response Centered at fMOD

The group delay of the filter is the time for a signal to propagate from the input to the output of the filter. Because the filter is a linear-phase design, the envelope of a multifrequency complex signal is undistorted by filter processing. The group delay (expressed in units of time) is constant versus signal frequency and is equal to 34 / fDATA. Be aware that after a step input is applied to the ADC inputs, fully settled data occurs 68 data periods later. Figure 7-17 shows the filter group delay (34 / fDATA) and the settling time for a step input (68 / fDATA).

ADS127L14 ADS127L18 Wideband Filter Step Response
 
Figure 7-17 Wideband Filter Step Response

The digital filter restarts when the ADC is synchronized. After synchronization, the filter discards the next 68 conversions to account for filter settling time. The Latency Time column of Table 7-7 lists the time for the first conversion to appear on the frame-sync port after synchronization. The latency time includes an initial overhead time for filter reset. The first data is fully settled data. If a step input occurs while continuously converting, then the next 69 conversions are partially settled data.

Table 7-2 Wideband Filter Characteristics
MODE fCLK
(MHz)		 OSR DATA RATE
(kSPS)		 –0.1dB FREQUENCY
(kHz)		 –3dB FREQUENCY
(kHz)		 LATENCY TIME(1)
(µs)
Max speed 32.768 32 512 211.2 223.9 134.2
High speed 25.6 400 165 174.96 171.8
Mid speed 12.8 200 82.5 87.48 343.5
Low speed 3.2 50 20.63 21.87 1374
Max speed 32.768 64 256 105.6 112.0 267.0
High speed 25.6 200 82.5 87.48 341.8
Mid speed 12.8 100 41.25 43.74 683.5
Low speed 3.2 25 10.31 10.94 2734
Max speed 32.768 128 128 52.8 55.99 532.0
High speed 25.6 100 41.25 43.74 681.0
Mid speed 12.8 50 20.63 21.87 1362
Low speed 3.2 12.5 5.1562 5.468 5448
Max speed 32.768 256 64 26.4 28.00 1064
High speed 25.6 50 20.625 21.87 1362
Mid speed 12.8 25 10.31 10.93 2724
Low speed 3.2 6.25 2.578 2.734 10895
Max speed 32.768 512 32 13.2 14.00 2126
High speed 25.6 25 10.312 10.935 2721
Mid speed 12.8 12.5 5.156 5.467 5443
Low speed 3.2 3.125 1.289 1.367 21770
Max speed 32.768 1024 16 6.6 7.998 4251
High speed 25.6 12.5 5.156 5.467 5441
Mid speed 12.8 6.25 2.578 2.734 10883
Low speed 3.2 1.5625 0.645 0.6834 43530
Max speed 32.768 2048 8 3.3 3.499 8501
High speed 25.6 6.25 2.578 2.734 10881
Mid speed 12.8 3.125 1.289 1.367 21762
Low speed 3.2 0.78125 0.322 0.3417 87050
Max speed 32.768 4096 4 1.65 1.750 17001
High speed 25.6 3.125 1.289 1.367 21761
Mid speed 12.8 1.5625 0.645 0.6834 43522
Low speed 3.2 0.390625 0.161 0.1709 174090
(1) Latency time increases by 8 / fCLK (µs) when the analog input buffers are enabled.