SBASAM0A March 2024 – June 2024 ADS127L18
ADVANCE INFORMATION
The device provides the option of programming through hardware mode (pin control) or by software (SPI mode). Hardware programming is selected by floating or grounding the MODE pin. In hardware control mode, the SPI is disabled and the device is configured by setting the programming pins to the desired level. Figure 7-41 and Table 7-16 describe the programming pin and mode functionality. Not all programing options are available in hardware mode. See the SPI Programming section for details of SPI programming.
The device reads the state of the programming pins one time at each power-up cycle and device reset. The three states are 1, 0 and float. Make sure the desired state of the pins are established prior to power-up cycle or reset events. To read the pins, the device cycles the pins high and low several times through a weak driver. If a float state is detected on a pin, the device drives the pin low to prevent the pin from floating during normal operation. After the pins are read, changes to the pins are not acknowledged until the next power or reset cycle.
Because the device cycles the pins during the read operation, external pin capacitance and leakage current for the float state are limited. In addition, maximum value of external pullup and pulldown resistance values for logic 1 and logic 0 states (if used) are limited. Figure 7-42 shows the pin condition limits. For proper operation, do not tie floated input pins from other devices together.
Table 7-16 shows the pin functions of the hardware programming mode.
PIN | NO. | DESCRIPTION | STATE(1) | FUNCTION | ||
---|---|---|---|---|---|---|
MODE | 54 | SPI or hardware programming mode | 0 | Hardware programming, all buffers on | ||
1 | SPI programming, program through SPI | |||||
F | Hardware programming, all buffers off | |||||
CS/SPEED | 55 | Speed mode | 0 | Low-speed mode | ||
1 | Max-speed mode | |||||
F | Mid-speed mode | |||||
SCLK/FLTR | 56 | Filter type | 0 | Wideband filter | ||
1 | Low-latency sinc4 filter | |||||
F | Low-latency sinc4 + sinc1 filter | |||||
SDO/OSR1 SDI/OSR0 |
2,1 | Filter OSR | OSR1/OSR0 | WIDEBAND FILTER | SINC4 FILTER | SINC4 + SINC1 FILTER |
00 | 32 | 12 | 64 | |||
01 | 64 | 16 | 128 | |||
0F | 128 | 24 | 320 | |||
10 | 256 | 32 | 640 | |||
11 | 512 | 64 | 1280 | |||
1F | 1024 | 128 | 3200 | |||
F0 | 2048 | 256 | 6400 | |||
F1 | 4096 | 1024 | 12800 | |||
FF | 4096 | 4096 | 32000 | |||
GPIO0/TDM | 3 | Data port TDM | 0 | No TDM, four or eight data lanes (all DOUTn pins are used) | ||
1 | TDM mode, one data lane (DOUT1 pin) | |||||
F | TDM mode, two data lanes (DOUT1 and DOUT2 pins) | |||||
GPIO1/HDR | 4 | Data-port header | 0 | 24 data bits (only) | ||
1 | STATUS header byte + 24 data bits | |||||
F | STATUS header byte + 24 data bits + CRC byte |
Programming options not available in hardware programming mode are assigned register default values. See the Register Map section for default values. Table 7-16 shows the hardware programming mode default value deviations from the register default values.
FUNCTION | HARDWARE MODE DEFAULT |
---|---|
Clock mode | External clock |
Reference range | High reference range |