SBASAM0A March 2024 – June 2024 ADS127L18
ADVANCE INFORMATION
To achieve data sheet performance, use a minimum four-layer PCB board with the inner layers dedicated to ground and power planes. Use one or more power planes to route the power supplies to the ADC. Best performance is achieved by combining the analog and digital grounds on a single, unbroken ground plane. In some layout geometries, however, separate analog and digital grounds are necessary to direct digital currents away from the analog ground. Digital currents include pulsing LED indicators, relays, and so on. In this case, consider separate ground return paths for these loads. When separate analog and digital grounds are used, join the grounds at the ADC.
The top and bottom layers route the analog and digital signals. Route the input signal as a matched differential pair throughout the signal chain to reduce differential noise coupling. Avoid crossing or adjacent placement of digital signals with the analog signals. Separate the ADC clock input signal from SPI and frame-sync signals to avoid coupling to the clock signal. The device pin placement minimizes the need to cross digital and analog signals.
Place the voltage reference close to the ADC. Orient the reference such that the reference ground pin is close to the ADC REFN pins. Furthermore, make a direct connection from the REFN pins to the reference ground pin. Place the reference input capacitor close to the ADC pins. Place the signal input bypass capacitors close to the ADC inputs. Preferably, optimize the location of the differential input capacitor over the location of the capacitors from each input to ground.
Figure 9-6 shows an ADS127L18 layout example. The analog input differential capacitors are 2.2nF C0G dielectric, ceramic style in 0402 size. The analog input common-mode capacitors are 220pF C0G dielectric in 0402 size. The differential input capacitors are placed closest to the device input pins. The analog input drivers originate from both top and bottom sides of the PCB to conserve space. The digital outputs are source-terminated with 10Ω resistors to impedance match to 50Ω traces. A four-layer PCB is used, with the inner layers dedicated as ground and power planes.