SBASAM0B March   2024  – November 2024 ADS127L18

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Clock Dividers
        2. 7.3.3.2 Internal Oscillator
        3. 7.3.3.3 External Clock
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 VCM Output Voltage
      6. 7.3.6 GPIO
      7. 7.3.7 Modulator
      8. 7.3.8 Digital Filter
        1. 7.3.8.1 Wideband Filter
        2. 7.3.8.2 Low-Latency Filter (Sinc)
          1. 7.3.8.2.1 Sinc4 Filter
          2. 7.3.8.2.2 Sinc4 + Sinc1 Cascade Filter
          3. 7.3.8.2.3 Sinc3 Filter
          4. 7.3.8.2.4 Sinc3 + Sinc1 Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1  Reset
        1. 7.4.1.1 RESET Pin
        2. 7.4.1.2 Reset by SPI Register
        3. 7.4.1.3 Reset by SPI Input Pattern
      2. 7.4.2  Idle and Standby Modes
      3. 7.4.3  Power-Down
      4. 7.4.4  Speed Modes
      5. 7.4.5  Synchronization
        1. 7.4.5.1 Synchronized Control Mode
        2. 7.4.5.2 Start/Stop Control Mode
      6. 7.4.6  Conversion-Start Delay Time
      7. 7.4.7  Calibration
        1. 7.4.7.1 Offset Calibration Registers
        2. 7.4.7.2 Gain Calibration Registers
        3. 7.4.7.3 Calibration Procedure
      8. 7.4.8  Data Averaging
      9. 7.4.9  Diagnostics
        1. 7.4.9.1 ERROR Pin and ERR_FLAG Bit
        2. 7.4.9.2 SPI CRC
        3. 7.4.9.3 Register Map CRC
        4. 7.4.9.4 ADC Error
        5. 7.4.9.5 SPI Address Range
        6. 7.4.9.6 SCLK Counter
        7. 7.4.9.7 Clock Counter
        8. 7.4.9.8 Frame-Sync CRC
        9. 7.4.9.9 Self Test
      10. 7.4.10 Frame-Sync Data Port
        1. 7.4.10.1  Data Packet
        2. 7.4.10.2  Data Format
        3. 7.4.10.3  STATUS_DP Header Byte
        4. 7.4.10.4  FSYNC Pin
        5. 7.4.10.5  DCLK Pin
        6. 7.4.10.6  DOUTx Pins
        7. 7.4.10.7  DINx Pins
        8. 7.4.10.8  Time Division Multiplexing
        9. 7.4.10.9  Daisy Chain
        10. 7.4.10.10 DOUTx Timing
    5. 7.5 Programming
      1. 7.5.1 Hardware Programming
      2. 7.5.2 SPI Programming
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output (SDO)
      3. 7.5.3 SPI Frame
      4. 7.5.4 Commands
        1. 7.5.4.1 Write Register Command
        2. 7.5.4.2 Read Register Command
      5. 7.5.5 SPI Daisy-Chain
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Antialias Filter
      3. 9.1.3 Reference Voltage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 AVDD1 and AVSS
      2. 9.3.2 AVDD2
      3. 9.3.3 IOVDD
      4. 9.3.4 CAPA and CAPD
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.3.8.2.1 Sinc4 Filter

The sinc4 filter performs averaging and decimation of the modulator data to produce data rates up to 1365.3kSPS in max-speed mode, 1066.6kSPS in high-speed mode, 533.3kSPS in mid-speed mode and 133.333kSPS in low-speed mode. Increasing the OSR value decreases the ADC data rate that reduces signal bandwidth and total noise resulting from increased data averaging and decimation.

Table 7-20 lists the sinc4 filter characteristics.

Table 7-3 Sinc4 Filter Characteristics
MODE fCLK
(MHz)		 OSR DATA RATE
(kSPS)		 –3-dB FREQUENCY
(kHz)		 LATENCY TIME
(μs)(1)
Max speed 32.768 12 1365.3 310.2 3.9
High speed 25.6 1066.6 242.3 5.1
Mid speed 12.8 533.3
 121.2 10.1
Low speed 3.2 133.33 30.3 40.5
Max speed 32.768 16 1024 232.7 4.9
High speed 25.6 800 181.8 6.3
Mid speed 12.8 400 90.9 12.6
Low speed 3.2 100 22.7 50.5
Max speed 32.768 24 682.67 155.1 6.9
High speed 25.6 533.3 121.2 8.9
Mid speed 12.8 266.67 60.6 17.1
Low speed 3.2 66.67 15.1 70.8
Max speed 32.768 32 512 116.3 8.9
High speed 25.6 400 90.9 11.4
Mid speed 12.8 200 45.4 22.8
Low speed 3.2 50 11.4 91.4
Max speed 32.768 64 256 58.2 16.6
High speed 25.6 200 45.4 21.3
Mid speed 12.8 100 22.7 42.6
Low speed 3.2 25 5.68 171
Max speed 32.768 128 128 29.1 32.3
High speed 25.6 100 22.7 41.3
Mid speed 12.8 50 11.4 82.6
Low speed 3.2 12.5 2.84 331
Max speed 32.768 256 64 14.5 63.6
High speed 25.6 50 11.4 81.4
Mid speed 12.8 25 5.68 163
Low speed 3.2 6.25 1.42 651
Max speed 32.768 512 32 7.27 126
High speed 25.6 25 5.68 162
Mid speed 12.8 12.5 2.84 324
Low speed 3.2 3.125 0.710 1294
Max speed 32.768 1024 16 3.64 251
High speed 25.6 12.5 2.84 321
Mid speed 12.8 6.25 1.42 643
Low speed 3.2 1.5625 0.355 2570
Max speed 32.768 2048 8 1.82 501
High speed 25.6 6.25 1.42 641
Mid speed 12.8 3.125 0.710 1282
Low speed 3.2 0.7813 0.178 5130
Max speed 32.768 4096 4 0.909 1001
High speed 25.6 3.125 0.710 1281
Mid speed 12.8 1.563 0.355 2562
Low speed 3.2 0.391 0.089 10250
(1) Latency time increases by 8 / fCLK (µs) when the analog input buffers are enabled.

Because the amount of data averaging is reduced for OSR values equal to 12, 16, and 24, full 24-bit output data resolution is not available. Table 7-4 summarizes the output data resolution for low OSR values.

Table 7-4 Sinc4 Data Resolution
OSR RESOLUTION (BITS)
12 19
16 20
24 23
≥32 24

Figure 7-18 and Figure 7-19 show the sinc4 frequency response for OSR = 32. The frequency response consists of a series of response nulls occurring at multiples of fDATA with a series of decaying peaks in between. At the null frequencies, the filter has zero gain. A folded image of the filter response appears when fIN/fDATA > OSR/2, as illustrated in the frequency plot of Figure 7-19 for OSR = 32. 0dB attenuation occurs at input frequencies near n × fMOD (n = 1, 2, 3, and so on). If signals are present at these frequencies, the signal is aliased to the pass band.

ADS127L14 ADS127L18 Sinc4 Frequency Response (OSR = 32)Figure 7-18 Sinc4 Frequency Response
(OSR = 32)
ADS127L14 ADS127L18 Sinc4 Frequency Response to fMOD (OSR = 32)Figure 7-19 Sinc4 Frequency Response to fMOD (OSR = 32)