SBASAM0B March   2024  – November 2024 ADS127L18

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Clock Dividers
        2. 7.3.3.2 Internal Oscillator
        3. 7.3.3.3 External Clock
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 VCM Output Voltage
      6. 7.3.6 GPIO
      7. 7.3.7 Modulator
      8. 7.3.8 Digital Filter
        1. 7.3.8.1 Wideband Filter
        2. 7.3.8.2 Low-Latency Filter (Sinc)
          1. 7.3.8.2.1 Sinc4 Filter
          2. 7.3.8.2.2 Sinc4 + Sinc1 Cascade Filter
          3. 7.3.8.2.3 Sinc3 Filter
          4. 7.3.8.2.4 Sinc3 + Sinc1 Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1  Reset
        1. 7.4.1.1 RESET Pin
        2. 7.4.1.2 Reset by SPI Register
        3. 7.4.1.3 Reset by SPI Input Pattern
      2. 7.4.2  Idle and Standby Modes
      3. 7.4.3  Power-Down
      4. 7.4.4  Speed Modes
      5. 7.4.5  Synchronization
        1. 7.4.5.1 Synchronized Control Mode
        2. 7.4.5.2 Start/Stop Control Mode
      6. 7.4.6  Conversion-Start Delay Time
      7. 7.4.7  Calibration
        1. 7.4.7.1 Offset Calibration Registers
        2. 7.4.7.2 Gain Calibration Registers
        3. 7.4.7.3 Calibration Procedure
      8. 7.4.8  Data Averaging
      9. 7.4.9  Diagnostics
        1. 7.4.9.1 ERROR Pin and ERR_FLAG Bit
        2. 7.4.9.2 SPI CRC
        3. 7.4.9.3 Register Map CRC
        4. 7.4.9.4 ADC Error
        5. 7.4.9.5 SPI Address Range
        6. 7.4.9.6 SCLK Counter
        7. 7.4.9.7 Clock Counter
        8. 7.4.9.8 Frame-Sync CRC
        9. 7.4.9.9 Self Test
      10. 7.4.10 Frame-Sync Data Port
        1. 7.4.10.1  Data Packet
        2. 7.4.10.2  Data Format
        3. 7.4.10.3  STATUS_DP Header Byte
        4. 7.4.10.4  FSYNC Pin
        5. 7.4.10.5  DCLK Pin
        6. 7.4.10.6  DOUTx Pins
        7. 7.4.10.7  DINx Pins
        8. 7.4.10.8  Time Division Multiplexing
        9. 7.4.10.9  Daisy Chain
        10. 7.4.10.10 DOUTx Timing
    5. 7.5 Programming
      1. 7.5.1 Hardware Programming
      2. 7.5.2 SPI Programming
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output (SDO)
      3. 7.5.3 SPI Frame
      4. 7.5.4 Commands
        1. 7.5.4.1 Write Register Command
        2. 7.5.4.2 Read Register Command
      5. 7.5.5 SPI Daisy-Chain
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Antialias Filter
      3. 9.1.3 Reference Voltage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 AVDD1 and AVSS
      2. 9.3.2 AVDD2
      3. 9.3.3 IOVDD
      4. 9.3.4 CAPA and CAPD
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at AVDD1 =  5V, AVDD2 = 1.8V to 5V, AVSS = 0V, IOVDD = 1.8V, VIN = 0V, VCM = 2.5V, VREFP =  4.096V, VREFN = 0V, high-reference range, 1x input range, all speed modes, all channels active, input precharge buffers on, and reference precharge buffer on (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS, MAX-SPEED MODE
Input current,
differential input voltage		 Input buffers off 125 µA/V
Input buffers off, 2x input range 60
Input buffers on ±2 µA
Input current drift,
differential input voltage		 Input buffers off 5 nA/V/°C
Input buffers off, 2x input range 2
Input buffers on 20 nA/°C
Input current,
common-mode input voltage		 Input buffers off 6.5 µA/V
Input buffers off, 2x input range 3
Input buffers on ±2 µA
ANALOG INPUTS, HIGH-SPEED MODE
Input current,
differential input voltage		 Input buffers off 95 µA/V
Input buffers off, 2x input range 47
Input buffers on ±1.5 µA
Input current drift,
differential input voltage		 Input buffers off 3 nA/V/°C
Input buffers off, 2x input range 1.5
Input buffers on 5 nA/°C
Input current,
common-mode input voltage		 Input buffers off 5 µA/V
Input buffers off, 2x input range 2.5
Input buffers on ±1.5 µA
ANALOG INPUTS, MID-SPEED MODE
Input current,
differential input voltage		 Input buffers off 47 µA/V
Input buffers off, 2x input range 25
Input buffers on ±1.5 µA
Input current drift,
differential input voltage		 Input buffers off 2 nA/V/°C
Input buffers off, 2x input range 1
Input buffers on 5 nA/°C
Input current,
common-mode input voltage		 Input buffers off 2.5 µA/V
Input buffers off, 2x input range 1.3
Input buffers on ±1.5 µA
ANALOG INPUTS, LOW-SPEED MODE
Input current,
differential input voltage		 Input buffers off 12 µA/V
Input buffers off, 2x input range 6
Input buffers on ±0.4 µA
Input current drift,
differential input voltage		 Input buffers off 1 nA/V/°C
Input buffers off, 2x input range 0.5
Input buffers on 0.2 nA/°C
Input current,
common-mode input voltage		 Input buffers off 0.6 µA/V
Input buffers off, 2x input range 0.3
Input buffers on ±0.4 µA
GENERAL CHARACTERISTICS
Resolution OSR ≥ 32 24 Bits
en DC Noise See the Noise Performance section for details
NMRR Normal-mode rejection ratio fIN = 50Hz (±1Hz), fDATA = 50SPS, sinc3 filter 100 dB
fIN = 60Hz (±1Hz), fDATA = 60SPS, sinc3 filter 100
MAX-SPEED MODE (fCLK = 32.768MHz)
fDATA Data rate Wideband filter 4 512 kSPS
Low-latency filter 0.1024 1365.3 kSPS
Offset error TA = 25°C –250 ±60 250 µV
Offset drift 25 150 nV/°C
Gain error TA = 25°C –2500 ±200 2500 ppm of FSR
Gain drift 1 3.0 ppm of FSR/°C
INL Integral nonlinearity (1) 4 6.5 ppm of FSR
DR Dynamic range Inputs shorted,
OSR = 64,
fDATA = 256kSPS		 Wideband filter 109.5 111.5 dB
Wideband filter,
VREF = 2.5V		 107.5
Wideband filter,
VREF = 2.5V,
2x input range		 108.5
Low-latency filter 112 114.5
Low-latency filter,
VREF = 2.5V		 110
Low-latency filter,
VREF = 2.5V,
2x input range		 111
SNR Signal-to-noise ratio fIN = 1kHz,
VIN = –0.2dBFS,
OSR = 64,
fDATA = 256kSPS
 		 Wideband filter 108.5 dB
Wideband filter,
VREF  = 2.5V		 105.5
Wideband filter,
VREF  = 2.5V,
2x input range		 106.5
Low-latency filter 111
Low-latency filter,
VREF = 2.5V		 108
Low-latency filter
VREF = 2.5V,
2x input range		 109
THD Total harmonic distortion fIN = 1kHz,
VIN = –0.2dBFS,
OSR = 64, 
fDATA = 200kSPS,
9 harmonics		 VREF = 2.5V –108 –99 dB
VREF = 4.096V –106 –100 dB
IMD Intermodulation distortion fIN = 9.7kHz and 10.3kHz,
VIN = –6.5dBFS		 Second-order terms –120 dB
Third-order terms –110
SFDR Spurious-free dynamic range fIN = 1kHz, VIN = –0.2dBFS, OSR = 64 110 dB
Crosstalk fIN = 1kHz, VIN = –0.2dbFS (3) –120 dB
CMRR Common-mode rejection ratio At dc 92 115 dB
Up to 10kHz 110
At dc, 2x input range 105
PSRR Power-supply rejection ratio AVDD1, dc 98 dB
AVDD2, dc 130
IOVDD, dc 108
HIGH-SPEED MODE (fCLK = 25.6MHz)
fDATA Data rate Wideband filter 3.125 400 kSPS
Low-latency filter 0.08 1067
Offset error TA = 25°C –200 ±30 200 µV
Offset drift 10 35 nV/°C
Gain error TA = 25°C –2500 ±200 2500 ppm of FSR
Gain drift 0.5 1.0 ppm of FSR/°C
INL Integral nonlinearity (1) 1 2.8 ppm of FSR
DR Dynamic range Inputs shorted,
OSR = 64,
fDATA = 200kSPS		 Wideband filter 110 112 dB
Wideband filter,
VREF = 2.5V		 108
Wideband filter,
VREF = 2.5V,
2x input range		 108.5
Low-latency filter 113 114.5
Low-latency filter,
VREF = 2.5V		 110.5
Low-latency filter,
VREF = 2.5V,
2x input range		 111
SNR Signal-to-noise ratio fIN = 1kHz,
VIN = –0.2dBFS,
OSR = 64,
fDATA = 200kSPS
 		 Wideband filter 110.5 dB
Wideband filter,
VREF = 2.5V		 106
Wideband filter,
VREF = 2.5V,
2x input range		 107.5
Low-latency filter 112.5
Low-latency filter,
VREF = 2.5V		 108.5
Low-latency filter,
VREF = 2.5V,
2x input range		 110
THD Total harmonic distortion
fIN = 1kHz,
VIN = –0.2dBFS,
OSR = 64, 
fDATA = 200kSPS,
9 harmonics		 VREF = 2.5V –118 –108 dB
VREF = 4.096V –118 –108 dB
IMD Intermodulation distortion fIN = 9.7kHz and 10.3kHz, VIN =  –6.5dBFS Second-order terms –125 dB
Third-order terms –115 dB
SFDR Spurious-free dynamic range fIN = 1kHz, VIN = –0.2dBFS, OSR = 64 120 dB
Crosstalk fIN = 1kHz, VIN = –0.2dbFS (3) –130 dB
CMRR Common-mode rejection ratio At dc 105 120 dB
Up to 10kHz 120
At dc, 2x input range 105
PSRR Power-supply rejection ratio AVDD1, dc 118 dB
AVDD2, dc 130
IOVDD, dc 113
MID-SPEED MODE (fCLK = 12.8MHz)
fDATA Data rate Wideband filter 1.5625 200 kSPS
Low-latency filter 0.08 533.3
Offset error TA = 25°C –150 ±30 150 µV
Offset drift 5 30 nV/°C
Gain error TA = 25°C –2500 ±200 2500 ppm of FSR
Gain drift 0.25 0.5 ppm of FSR/°C
INL Integral nonlinearity (1) 0.6 1.8 ppm of FSR
DR Dynamic range Inputs shorted,
OSR = 64,
fDATA = 100kSPS		 Wideband filter 110 112 dB
Wideband filter,
VREF = 2.5V		 108.5
Wideband filter,
VREF = 2.5V
2x input range		 108.5
Low-latency filter 112.5 114.5
Low-latency filter,
VREF = 2.5V		 111
Low-latency filter,
VREF = 2.5V,
2x input range		 111
SNR Signal-to-noise ratio fIN = 1kHz,
VIN = –0.2dbFS,
OSR = 64,
fDATA = 100kSPS
 		 Wideband filter 110.5 dB
Wideband filter,
VREF = 2.5V		 106.5
Wideband filter,
VREF = 2.5V,
2x input range		 108
Low-latency filter 113
Low-latency filter,
VREF = 2.5V		 109
Low-latency filter,
VREF = 2.5V,
2x input range		 110.5
THD Total harmonic distortion fIN =  1kHz,
VIN = –0.2dBFS,
OSR = 64, 
fDATA = 200kSPS,
9 harmonics		 VREF = 2.5V –125 –118 dB
VREF = 4.096V –122 –116 dB
IMD Intermodulation distortion fIN = 9.7kHz and 10.3kHz, VIN = –6.5dbFS Second-order terms –125 dB
Third-order terms –115
SFDR Spurious-free dynamic range fIN = 1kHz, VIN = –0.2dbFS, OSR = 64 123 dB
Crosstalk fIN = 1kHz, VIN = –0.2dbFS (3) –130 dB
CMRR Common-mode rejection ratio At dc 114 125 dB
Up to 10kHz 120
At dc, 2x input range 105
PSRR Power-supply rejection ratio AVDD1, dc 125 dB
AVDD2, dc 130
IOVDD, dc 112
LOW-SPEED MODE (fCLK = 3.2MHz)
fDATA Data rate Wideband filter 0.390625 50 kSPS
Low-latency filter 0.01 133.3
Offset error TA = 25°C –150 ±30 150 µV
Offset drift 5 30 nV/°C
Gain error TA = 25°C –2500 ±200 2500 ppm of FSR
Gain drift 0.25 0.6 ppm of FSR/°C
INL Integral nonlinearity (1) 0.6 1.4 ppm of FSR
DR Dynamic range Inputs shorted,
OSR = 64,
fDATA = 25kSPS		 Wideband filter 110 112 dB
Wideband filter,
VREF = 2.5V		 108
Wideband filter,
VREF = 2.5V,
2x input range		 109
Low-latency filter 112.5 115
Low-latency filter,
VREF = 2.5V		 110.5
Low-latency filter,
VREF = 2.5V,
2x input range		 111.5
SNR Signal-to-noise ratio fIN = 1kHz,
VIN = –0.2dBFS,
OSR = 64,
fDATA = 25kSPS		 Wideband filter 111 dB
Wideband filter,
VREF = 2.5V		 107
Wideband filter,
VREF = 2.5V,
2x input range		 108.5
Low-latency filter 113.5
Low-latency filter,
VREF = 2.5V		 109.5
Low-latency filter,
VREF = 2.5V,
2x input range		 111
THD Total harmonic distortion fIN = 1kHz,
VIN = –0.2dBFS,
OSR = 64,
fDATA = 25kSPS,
9 harmonics		 VREF = 2.5V –125 –118 dB
VREF = 4.096V –125 –118 dB
IMD Intermodulation distortion fIN = 9.7kHz and 10.3kHz, VIN = –6.5dBFS Second-order terms –125 dB
Third-order terms –120 dB
SFDR Spurious-free dynamic range fIN = 1kHz, VIN = –0.2dBFS, OSR = 64 125 dB
Crosstalk fIN = 1kHz, VIN = –0.2dbFS (3) –130 dB
CMRR Common-mode rejection ratio At dc 118 130 dB
Up to 10kHz 120
At dc, 2x input range 105
PSRR Power-supply rejection ratio AVDD1, dc 125 dB
AVDD2, dc 125
IOVDD, dc 110
WIDEBAND FILTER CHARACTERISTICS
Pass-band frequency Within envelope of pass-band ripple 0.4 ∙ fDATA Hz
–0.1dB frequency 0.4125 ∙ fDATA
–3dB frequency 0.4374 ∙ fDATA
Pass-band ripple –0.0004 0.0004 dB
Stop-band frequency At stop-band attenuation 0.5 · fDATA Hz
Stop-band attenuation (2) 106 dB
Group delay 34 / fDATA s
Settling time 68 / fDATA s
VOLTAGE REFERENCE INPUTS
REFP and REFN input current REFP buffer off Max-speed mode 225 µA/V/ch
High-speed mode 190
Mid-speed mode 130
Low-speed mode 80
REFP input current REFP buffer on ±3 µA/ch
REFP and REFN
input current drift		 REFP buffer off Max-speed mode 20 nA/℃/ch
High-speed mode 20
Mid-speed mode 15
Low-speed mode 15
REFP input current drift REFP buffer on 10 nA/℃/ch
INTERNAL OSCILLATOR
fOSC Oscillator frequency 25.4 25.6 25.8 MHz
VCM OUTPUT VOLTAGE
Output voltage (AVDD1 + AVSS) / 2 V
Accuracy –1% ±0.1% 1%
Voltage noise 1kHz bandwidth 25 µVRMS
Start-up time CL = 100nF 1 ms
Capacitive load 100 nF
Resistive load 2 kΩ
Short-circuit current limit 10 mA
DIGITAL INPUTS/OUTPUTS
VIL Logic-low input level 0.3 IOVDD V
VIH Logic-high input level 0.7 IOVDD V
ILEAK External leakage current Tri-state pins, floating input state -5 5 µA
CLOAD Capacitive load Tri-state pins, floating input state 50 pF
REXT Pull-up or pull-down resistance Tri-state pins, logic low or high state 0 3 kΩ
VOL Logic-low output level OUT_DRV = 0b, IOL = 2mA 0.2 ∙ IOVDD V
OUT_DRV = 1b, IOL = 1mA 0.2 ∙ IOVDD
VOH Logic-high output level OUT_DRV = 0b, IOH = –2mA 0.8 ∙ IOVDD V
OUT_DRV = 1b, IOH = –1mA 0.8 ∙ IOVDD
ERROR pin, IOH = –2µA 0.8 ∙ IOVDD
Input hysteresis 150 mV
Input current –1 1 µA
ANALOG SUPPLY CURRENT
IAVDD1, IAVSS AVDD1, AVSS current
(buffers off)		 One channel Max-speed mode 1.9 2.1 mA
Each additional channel 1.7 2.0 mA/ch
One channel High-speed mode 1.5 1.7 mA
Each additional channel 1.3 1.6 mA/ch
One channel Mid-speed mode 0.9 1.0 mA
Each additional channel 0.7 0.85 mA/ch
One Channel Low-speed mode 0.3 0.35 mA
Each additional channel 0.2 0.21 mA/ch
Standby mode 110 µA
Power-down mode 5 µA
AVDD1, AVSS buffer current Input buffers Max-speed mode 1.78 2.1 mA/buffer
High-speed mode 1.36 1.6
Mid-speed mode 0.7 0.85
Low-speed mode 0.2 0.25
REFP buffers Max-speed mode 1.6 1.7 mA/buffer
High-speed mode 1.5 1.65
Mid-speed mode 0.9 1.0
Low-speed mode 0.4 0.5
VCM buffer 0.1 mA
IAVDD2, IAVSS AVDD2, AVSS current Max-speed mode 4.6 5.1 mA/ch
High-speed mode 3.6 4.0
Mid-speed mode 2.3 2.55
Low-speed mode 0.85 0.96
Standby mode 60 µA
Power-down mode 1 µA
DIGITAL SUPPLY CURRENT
IIOVDD IOVDD current Wideband filter
OSR = 32		 Max-speed mode 2.1 2.5 mA/ch
High-speed mode 1.6 2.0
Mid-speed mode 0.8 1
Low-speed mode 0.2 0.35
Low-latency filter
OSR = 32		 Max-speed mode 0.6 0.8
High-speed mode 0.5 0.7
Mid-speed mode 0.20 0.35
Low-speed mode 0.05 0.15
Standby mode External clock 15 µA
Internal oscillator 50
Power-down mode 35 µA
POWER DISSIPATION
PD Power dissipation ADS127L14
wideband filter,
AVDD2 = 1.8V,
buffers off		 Max-speed mode 83 95 mW
High-speed mode 64 76
Mid-speed mode 37 43
Low-speed mode 12 14
ADS127L14
low-latency filter,
AVDD2 = 1.8V,
buffers off		 Max-speed mode 72 83
High-speed mode 57 66
Mid-speed mode 33 39
Low-speed mode 11 13
ADS127L18
wideband filter,
AVDD2 = 1.8V,
buffers off		 Max-speed mode 165 190 mW
High-speed mode 128 151
Mid-speed mode 74 86
Low-speed mode 24 28
ADS127L18
low-latency filter,
AVDD2 = 1.8V,
buffers off		 Max-speed mode 144 165
High-speed mode 112 132
Mid-speed mode 65 77
Low-speed mode 21 25
(1) Best-fit method.
(2) Stop-band attenuation as provided by the digital filter. Input frequencies in the stop band intermodulate with the chop frequency beginning at fMOD / 32, which results in stop-band attenuation <106dB. See the Stop-Band Attenuation figure for details.
(3) Crosstalk measured on one shorted-input channel with three (ADS127L14) and seven (ADS127L18) active channels.