SBASAK4B March 2023 – April 2024 ADS127L21
PRODUCTION DATA
The ADC has the option of 3-wire SPI operation by grounding CS. Engage 3-wire mode by grounding CS at power up or after reset. The 3-wire SPI mode is indicated by bit 7 (CS_MODE) of the STATUS register. The device changes to 4-wire SPI mode when CS is taken high.
Because CS no longer controls the frame timing in 3-wire mode, SCLKs are counted by the ADC to determine the frame beginning and end. Make sure the number of SCLK bits are controlled by the host and match the size of the output frame. The number of bits per frame depends on the device configuration. The size of the output frame is given in Table 7-15. Because frame timing is determined by the number of SCLKs, avoid inadvertent SCLK transitions, such as those occurring at power up.
The 3-wire SPI mode supports the same command format and clocking as 4-wire mode, except there is no CS toggling. There are no wait time requirements between frames for the remaining registers. Except for read/write operations of the programmable filter coefficients, where a 10fCLK cycle delay is required between frames.