SBASAK4B March   2023  – April 2024 ADS127L21

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements (1.65 V ≤ IOVDD ≤ 2 V)
    7. 5.7  Switching Characteristics (1.65 V ≤ IOVDD ≤ 2 V)
    8. 5.8  Timing Requirements (2 V < IOVDD ≤ 5.5 V)
    9. 5.9  Switching Characteristics (2 V < IOVDD ≤ 5.5 V)
    10. 5.10 Timing Diagrams
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Internal Oscillator
        2. 7.3.3.2 External Clock
      4. 7.3.4 Modulator
      5. 7.3.5 Digital Filter
        1. 7.3.5.1 Wideband Filter
          1. 7.3.5.1.1 Wideband Filter Options
          2. 7.3.5.1.2 Sinc5 Filter Stage
          3. 7.3.5.1.3 FIR1 Filter Stage
          4. 7.3.5.1.4 FIR2 Filter Stage
          5. 7.3.5.1.5 FIR3 Filter Stage
          6. 7.3.5.1.6 FIR3 Default Coefficients
          7. 7.3.5.1.7 IIR Filter Stage
            1. 7.3.5.1.7.1 IIR Filter Stability
        2. 7.3.5.2 Low-Latency Filter (Sinc)
          1. 7.3.5.2.1 Sinc3 and Sinc4 Filters
          2. 7.3.5.2.2 Sinc3 + Sinc1 and Sinc4 + Sinc1 Cascade Filter
      6. 7.3.6 Power Supplies
        1. 7.3.6.1 AVDD1 and AVSS
        2. 7.3.6.2 AVDD2
        3. 7.3.6.3 IOVDD
        4. 7.3.6.4 Power-On Reset (POR)
        5. 7.3.6.5 CAPA and CAPD
      7. 7.3.7 VCM Output Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Speed Modes
      2. 7.4.2 Idle Mode
      3. 7.4.3 Standby Mode
      4. 7.4.4 Power-Down Mode
      5. 7.4.5 Reset
        1. 7.4.5.1 RESET Pin
        2. 7.4.5.2 Reset by SPI Register Write
        3. 7.4.5.3 Reset by SPI Input Pattern
      6. 7.4.6 Synchronization
        1. 7.4.6.1 Synchronized Control Mode
        2. 7.4.6.2 Start/Stop Control Mode
        3. 7.4.6.3 One-Shot Control Mode
      7. 7.4.7 Conversion-Start Delay Time
      8. 7.4.8 Calibration
        1. 7.4.8.1 OFFSET2, OFFSET1, OFFSET0 Calibration Registers (Addresses 0Ch, 0Dh, 0Eh)
        2. 7.4.8.2 GAIN2, GAIN1, GAIN0 Calibration Registers (Addresses 0Fh, 10h, 11h)
        3. 7.4.8.3 Calibration Procedure
    5. 7.5 Programming
      1. 7.5.1 Serial Interface (SPI)
        1. 7.5.1.1  Chip Select (CS)
        2. 7.5.1.2  Serial Clock (SCLK)
        3. 7.5.1.3  Serial Data Input (SDI)
        4. 7.5.1.4  Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.1.5  SPI Frame
        6. 7.5.1.6  Full-Duplex Operation
        7. 7.5.1.7  Device Commands
          1. 7.5.1.7.1 No-Operation
          2. 7.5.1.7.2 Read Register Command
          3. 7.5.1.7.3 Write Register Command
        8. 7.5.1.8  Read Conversion Data
          1. 7.5.1.8.1 Conversion Data
          2. 7.5.1.8.2 Data Ready
            1. 7.5.1.8.2.1 DRDY
            2. 7.5.1.8.2.2 SDO/DRDY
            3. 7.5.1.8.2.3 DRDY Bit
            4. 7.5.1.8.2.4 Clock Counting
          3. 7.5.1.8.3 STATUS Byte
        9. 7.5.1.9  Daisy-Chain Operation
        10. 7.5.1.10 3-Wire SPI Mode
          1. 7.5.1.10.1 3-Wire SPI Mode Frame Reset
        11. 7.5.1.11 SPI CRC
      2. 7.5.2 Register Memory CRC
        1. 7.5.2.1 Main Program Memory CRC
        2. 7.5.2.2 FIR Filter Coefficient CRC
        3. 7.5.2.3 IIR Filter Coefficient CRC
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 SPI Operation
      2. 9.1.2 Input Driver
      3. 9.1.3 Antialias Filter
      4. 9.1.4 Reference Voltage
      5. 9.1.5 Simultaneous-Sampling Systems
    2. 9.2 Typical Applications
      1. 9.2.1 A-Weighting Filter Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 PGA855 Programmable Gain Amplifier
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 THS4551 Antialias Filter Design
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.13 Noise Performance

The ADC provides four operational speed modes that provide trade-offs between ADC resolution, power consumption, and signal bandwidth. The modes are max speed, high speed, mid speed, and low speed, with decreasing orders of device power consumption. The wideband filter offers data rates up to 512kSPS (max-speed mode), 400kSPS (high-speed mode), 200kSPS (mid-speed mode), and 50kSPS (low-speed mode). Data are also accessible from the partial filters of the intermediate FIR1 or FIR2 stages for reduced filter time latency.

The low-latency sinc4 filter offers data rates up to 1.365MSPS (max-speed mode), 1.066MSPS (high-speed mode), 533kSPS (mid-speed mode), and 133kSPS (low-speed mode).

The programmable oversampling ratio (OSR) determines the output data rate and signal bandwidth, therefore affecting total noise performance. Increasing the OSR lowers the signal bandwidth and total noise by averaging more samples from the modulator to yield one conversion result.

Table 7-12 through Table 6-5 summarize the noise performance of the filters. Noise performance is specified for the 1x input range and a 4.096V reference voltage. In comparison, decreasing the reference voltage to 2.5V decreases dynamic range by 4dB (typical). 2.5V reference voltage and 2x input range operation decreases dynamic range by 3dB (typical) compared to a 4.096V reference voltage and 1x input range operation.

Noise data are the result of the standard deviation (rms) of the conversion data with inputs shorted and biased to the mid-supply voltage. Noise data are representative of typical performance at TA = 25°C. A minimum of 1,000 or 10 seconds of consecutive conversions (whichever occurs first) are used to measure RMS noise (en). Because of the statistical nature of noise, repeated noise measurements potentially yield higher or lower noise results.

Equation 13 converts RMS noise to dynamic range. Equation 25 converts RMS noise to effective resolution.

Equation 13. Dynamic Range (dB) = 20 · log10[FSR / (2 · √2 · en)]
Equation 14. Effective Resolution (bits) = log2(FSR / en)

where:

  • FSR = 2 · VREF (1x input range)
  • FSR = 4 · VREF (2x input range)
  • en = Noise voltage (RMS)

When evaluating ADC noise performance, consider the effect of the external buffer and amplifier noise to the total noise performance. The noise performance of the ADC is evaluated in isolation of the amplifiers by selecting the input short test connection of the input multiplexer.

Table 6-1 Wideband Filter Noise Performance (VREF = 4.096V, 1x Input Range)
MODE fCLK
(MHz)		 OSR DATA RATE
(kSPS)		 NOISE
(en, µVRMS)		 DYNAMIC RANGE
(dB)		 EFFECTIVE RESOLUTION
(Bits)
Max speed 32.768 32 512 11.1 108.3 19.5
High speed 25.6 400 10.9 108.5 19.5
Mid speed 12.8 200 10.6 108.7 19.6
Low speed 3.2 50 10.4 108.9 19.6
Max speed 32.768 64 256 7.64 111.6 20.0
High speed 25.6 200 7.50 111.7 20.1
Mid speed 12.8 100 7.30 112.0 20.1
Low speed 3.2 25 7.14 112.2 20.1
Max speed 32.768 128 128 5.34 114.7 20.5
High speed 25.6 100 5.25 114.8 20.6
Mid speed 12.8 50 5.07 115.1 20.6
Low speed 3.2 12.5 4.97 115.3 20.7
Max speed 32.768 256 64 3.79 117.7 21.0
High speed 25.6 50 3.72 117.8 21.1
Mid speed 12.8 25 3.58 118.2 21.1
Low speed 3.2 6.25 3.53 118.3 21.1
Max speed 32.768 512 32 2.71 120.6 21.5
High speed 25.6 25 2.67 120.7 21.5
Mid speed 12.8 12.5 2.54 121.2 21.6
Low speed 3.2 3.125 2.47 121.4 21.7
Max speed 32.768 1024 16 1.88 123.8 22.1
High speed 25.6 12.5 1.87 123.8 22.1
Mid speed 12.8 6.25 1.82 124.0 22.1
Low speed 3.2 1.5625 1.76 124.3 22.2
Max speed 32.768 2048 8 1.34 126.7 22.5
High speed 25.6 6.25 1.32 126.8 22.5
Mid speed 12.8 3.125 1.29 127.0 22.6
Low speed 3.2 0.78125 1.25 127.3 22.6
Max speed 32.768 4096 4 0.96 129.6 23.0
High speed 25.6 3.125 0.95 129.7 23.0
Mid speed 12.8 1.5625 0.93 129.9 23.1
Low speed 3.2 0.390625 0.89 130.3 23.1
Table 6-2 Sinc3 and Sinc4 Filter Noise Performance (VREF = 4.096V, 1x Input Range)
MODE fCLK
(MHz)		 OSR DATA RATE
(kSPS)		 NOISE
(en, µVRMS)(1)		 DYNAMIC RANGE
(dB)		 EFFECTIVE RESOLUTION (Bits)
SINC3 SINC4 SINC3 SINC4 SINC3 SINC4
Max speed 32.768 12 1365.3 239 66.8 81.7 92.7 15.1 16.9
High speed 25.6 1066.6 235 66.6 81.8 92.8 15.1 16.9
Mid speed 12.8 533.3 235 63.8 81.8 93.1 15.1 17.0
Low speed 3.2 133.33 232 63.1 81.9 93.2 15.1 17.0
Max speed 32.768 16 1024 99.9 24.8 89.2 101.3 16.3 18.3
High speed 25.6 800 99.6 24.5 89.3 101.5 16.3 18.4
Mid speed 12.8 400 98.9 24.5 89.3 101.5 16.3 18.4
Low speed 3.2 100 96.0 24.3 89.6 101.5 16.4 18.4
Max speed 32.768 24 682.67 31.1 10.8 99.4 108.6 18.0 19.5
High speed 25.6 533.3 31.0 10.3 99.4 108.9 18.0 19.6
Mid speed 12.8 266.67 30.8 10.1 99.5 109.2 18.0 19.6
Low speed 3.2 66.67 30.7 9.96 99.5 109.3 18.0 19.6
Max speed 32.768 32 512 15.2 8.24 105.6 110.9 19.0 19.9
High speed 25.6 400 15.0 8.07 105.7 111.1 19.1 20.0
Mid speed 12.8 200 14.8 7.88 105.8 111.3 19.1 20.0
Low speed 3.2 50 14.7 7.76 105.9 111.4 19.1 20.0
Max speed 32.768 64 256 6.20 5.71 113.4 114.1 20.3 20.5
High speed 25.6 200 6.15 5.53 113.5 114.4 20.3 20.5
Mid speed 12.8 100 5.98 5.42 113.7 114.6 20.4 20.5
Low speed 3.2 25 5.78 5.24 114.0 114.9 20.4 20.6
Max speed 32.768 128 128 4.21 3.98 116.8 117.2 20.9 21.0
High speed 25.6 100 4.16 3.89 116.9 117.4 20.9 21.0
Mid speed 12.8 50 4.10 3.75 117.0 117.8 20.9 21.1
Low speed 3.2 12.5 3.99 3.72 117.2 117.8 21.0 21.1
Mid speed 12.8 167 38.323 3.56 3.39 118.2 118.6 21.1 21.2
Max speed 32.768 256 64 2.99 2.78 119.7 120.4 21.4 21.5
High speed 25.6 50 2.95 2.74 119.8 120.5 21.4 21.5
Mid speed 12.8 25 2.87 2.69 120.1 120.6 21.4 21.5
Low speed 3.2 6.25 2.81 2.61 120.3 120.9 21.5 21.6
Max speed 32.768 333 49.201 2.67 2.50 120.7 121.3 21.5 21.6
High speed 25.6 38.438 2.59 2.46 121.0 121.4 21.6 21.7
Mid speed 12.8 19.219 2.53 2.43 121.2 121.5 21.6 21.7
Low speed 3.2 4.804 2.46 2.33 121.4 121.9 21.7 21.7
Max speed 32.768 512 32 2.11 1.98 122.8 123.3 21.9 22.0
High speed 25.6 25 2.09 1.93 122.8 123.5 21.9 22.0
Mid speed 12.8 12.5 2.01 1.88 123.2 123.8 22.0 22.1
Low speed 3.2 3.125 1.96 1.67 123.4 124.8 22.0 22.2
Max speed 32.768 667 24.564 1.90 1.77 123.7 124.3 22.0 22.1
High speed 25.6 19.19 1.86 1.75 123.8 124.4 22.1 22.2
Mid speed 12.8 9.595 1.82 1.67 124.0 124.8 22.1 22.2
Low speed 3.2 2.39 1.77 1.65 124.3 124.9 22.1 22.2
Max speed 32.768 1024 16 1.50 1.41 125.7 126.3 22.4 22.5
High speed 25.6 12.5 1.47 1.40 125.9 126.3 22.4 22.5
Mid speed 12.8 6.25 1.43 1.34 126.1 126.7 22.4 22.5
Low speed 3.2 1.56 1.42 1.31 126.2 126.9 22.5 22.6
Max speed 32.768 1333 12.291 1.36 1.25 126.6 127.3 22.5 22.6
High speed 25.6 9.602 1.34 1.23 126.7 127.4 22.5 22.7
Mid speed 12.8 4.801 1.29 1.19 127.0 127.7 22.6 22.7
Low speed 3.2 1.2 1.24 1.17 127.4 127.9 22.7 22.7
Max speed 32.768 2048 8 1.06 1.00 128.7 129.2 22.9 23.0
High speed 25.6 6.25 1.05 0.995 128.8 129.3 22.9 23.0
Mid speed 12.8 3.125 1.02 0.952 129.1 129.7 22.9 23.0
Low speed 3.2 0.78 0.969 0.935 129.5 129.8 23.0 23.1
Max speed 32.768 2667 6.143 0.967 0.890 129.5 130.3 23.0 23.1
High speed 25.6 4.799 0.949 0.858 129.7 130.6 23.0 23.2
Mid speed 12.8 2.4 0.913 0.867 130.0 130.5 23.1 23.2
Low speed 3.2 0.6 0.914 0.844 130.0 130.7 23.1 23.2
Max speed 32.768 4096 4 0.751 0.710 131.7 132.2 23.4 23.5
High speed 25.6 3.125 0.752 0.709 131.7 132.2 23.4 23.5
Mid speed 12.8 1.563 0.725 0.681 132.0 132.6 23.4 23.5
Low speed 3.2 0.39 0.709 0.649 132.2 133.0 23.5 23.6
Max speed 32.768 5333 3.072 0.697 0.630 132.4 133.3 23.5 23.6
High speed 25.6 2.4 0.676 0.626 132.6 133.3 23.5 23.6
Low speed 3.2 0.3 0.661 0.604 132.8 133.6 23.6 23.7
Mid speed 12.8 13333 0.437 0.410 0.60 136.3 137.0 24.2 24.3
Mid speed 12.8 16000 0.400 0.392 0.356 137.4 138.2 24.3 24.5
Max speed 32.768 26667 0.614 0.335 0.320 138.7 139.4 24.5 24.6
High speed 25.6 0.480 0.330 0.311 138.9 139.1 24.6 24.7
Low speed 3.2 0.06 0.316 0.290 139.2 140.0 24.7 24.8
Max speed 32.768 32000 0.512 0.309 0.303 139.4 139.6 24.7 24.7
High speed 25.6 0.4 0.306 0.294 139.5 139.9 24.7 24.7
Low speed 3.2 0.05 0.290 0.275 140.0 140.5 24.8 24.8
Mid speed 12.8 48000 0.133 0.251 0.274 141.2 140.5 25.0 24.8
Mid speed 12.8 80000 0.08 0.233 0.208 141.9 142.9 25.1 25.2
Max speed 32.768 96000 0.17067 0.238 0.202 141.7 143.1 25.0 25.3
High speed 25.6 0.133 0.186 0.250 143.8 141.3 25.4 25.0
Low speed 3.2 0.0167 0.245 0.207 141.5 142.9 25.0 25.2
Max speed 32.768 160000 0.102 0.243 0.243 141.5 141.5 25.0 25.0
High speed 25.6 0.08 0.232 0.242 141.9 141.6 25.1 25.0
Low speed 3.2 0.01 0.243 0.177 141.5 144.3 25.0 25.5
(1) High OSR values can yield varying noise results because of the limits of 24-bit quantization: 4.096 V / 223 = 0.488μV / code.
Table 6-3 Sinc3 + Sinc1 and Sinc4 + Sinc1 Filter Noise Performance (VREF = 4.096V, 1x Input Range)
MODE fCLK
(MHz)		 OSR
 DATA RATE
(SPS)		 NOISE
(en, µVRMS)(1)		 DYNAMIC RANGE
(dB)		 EFFECTIVE RESOLUTION (Bits)
Mid speed 12.8 13333 480 0.573 134.1 23.8
Mid speed 12.8 16000 400 0.533 134.7 23.9
Max speed 32.768 26656 614 0.419 136.8 24.2
High speed 25.6 480 0.416 136.9 24.2
Low speed 3.2 60 0.413 136.9 24.2
Max speed 32.768 32000 512 0.409 137.0 24.3
High speed 25.6 400 0.387 137.5 24.3
Low speed 3.2 50 0.362 138.1 24.4
Mid speed 12.8 48000 133 0.321 139.1 24.6
Mid speed 12.8 80000 80 0.274 140.5 24.8
Max speed 32.768 96000 170.6 0.254 141.1 24.9
High speed 25.6 133 0.256 141.1 24.9
Low speed 3.2 16.7 0.251 141.2 25.0
Max speed 32.768 160000 102.44 0.202 143.1 25.3
High speed 25.6 80 0.187 143.8 25.4
Low speed 3.2 10 0.201 143.2 25.3
(1) High OSR values can yield varying noise results because of the limits of 24-bit quantization: 4.096V / 223 = 0.488μV / code. Sinc3 + sinc1 and sinc4 + sinc1 filters yield equal noise performance.
Table 6-4 FIR1 Filter Noise Performance (VREF = 4.096V, 1x Input Range)
MODE fCLK
(MHz)		 OSR DATA RATE
(kSPS)		 NOISE
(en, µVRMS)		 DYNAMIC RANGE
(dB)		 EFFECTIVE RESOLUTION
(Bits)
Max speed 32.768 8 2048 641 73.1 13.6
High speed 25.6 1600 648 73.0 13.6
Mid speed 12.8 800 662 72.8 13.6
Low speed 3.2 200 681 72.6 13.6
Max speed 32.768 16 1024 93.0 89.9 16.4
High speed 25.6 800 94.8 89.7 16.4
Mid speed 12.8 400 99.9 89.2 16.3
Low speed 3.2 100 105 88.8 16.2
Max speed 32.768 32 512 11.0 108.4 19.5
High speed 25.6 400 10.8 108.6 19.5
Mid speed 12.8 200 10.5 108.8 19.6
Low speed 3.2 50 10.3 109.0 19.6
Max speed 32.768 64 256 7.44 111.8 20.1
High speed 25.6 200 7.30 112.0 20.1
Mid speed 12.8 100 7.09 112.2 20.1
Low speed 3.2 25 6.93 112.4 20.2
Max speed 32.768 128 128 5.20 114.9 20.6
High speed 25.6 100 5.10 115.1 20.6
Mid speed 12.8 50 4.93 115.4 20.7
Low speed 3.2 12.5 4.82 115.6 20.7
Max speed 32.768 256 64 3.69 117.9 21.1
High speed 25.6 50 3.63 118.0 21.1
Mid speed 12.8 25 3.48 118.4 21.2
Low speed 3.2 6.25 3.39 118.6 21.2
Max speed 32.768 512 32 2.64 120.8 21.6
High speed 25.6 25 2.62 120.9 21.6
Mid speed 12.8 12.5 2.47 121.4 21.7
Low speed 3.2 3.125 1.27 127.1 22.6
Max speed 32.768 1024 16 1.94 123.5 22.0
High speed 25.6 12.5 1.90 123.6 22.0
Mid speed 12.8 6.25 1.76 124.3 22.2
Low speed 3.2 1.5625 0.886 130.3 23.1
Table 6-5 FIR2 Filter Performance (VREF = 4.096V, 1x Input Range)
MODE fCLK
(MHz)		 OSR DATA RATE
(kSPS)		 NOISE
(en, µVRMS)		 DYNAMIC RANGE
(dB)		 EFFECTIVE RESOLUTION
(Bits)
Max speed 32.768 16 1024 51.0 95.1 17.3
High speed 25.6 800 51.0 95.1 17.3
Mid speed 12.8 400 50.3 95.2 17.3
Low speed 3.2 100 50.0 95.3 17.3
Max speed 32.768 32 512 11.6 108.0 19.4
High speed 25.6 400 11.4 108.1 19.5
Mid speed 12.8 200 11.1 108.3 19.5
Low speed 3.2 50 10.9 108.5 19.5
Max speed 32.768 64 256 7.85 111.3 20.0
High speed 25.6 200 7.69 111.5 20.0
Mid speed 12.8 100 7.47 111.8 21.1
Low speed 3.2 25 7.33 111.9 21.1
Max speed 32.768 128 128 5.47 114.5 20.5
High speed 25.6 100 5.36 114.7 20.5
Mid speed 12.8 50 5.18 114.9 20.6
Low speed 3.2 12.5 5.07 115.1 20.6
Max speed 32.768 256 64 3.86 117.5 21.0
High speed 25.6 50 3.80 117.6 21.0
Mid speed 12.8 25 3.66 118.0 21.1
Low speed 3.2 6.25 3.58 118.2 21.1
Max speed 32.768 512 32 2.79 120.3 21.5
High speed 25.6 25 2.73 120.5 21.5
Mid speed 12.8 12.5 2.59 121.0 21.6
Low speed 3.2 3.125 1.76 124.3 22.2
Max speed 32.768 1024 16 2.01 123.2 22.0
High speed 25.6 12.5 1.99 123.3 22.0
Mid speed 12.8 6.25 1.83 124.0 22.1
Low speed 3.2 1.5625 1.26 127.2 22.6
Max speed 32.768 2048 8 1.51 125.6 22.4
High speed 25.6 6.25 1.48 125.8 22.4
Mid speed 12.8 3.125 0.928 129.9 23.1
Low speed 3.2 0.78125 0.927 129.9 23.1