SBASAK4B March   2023  – April 2024 ADS127L21

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements (1.65 V ≤ IOVDD ≤ 2 V)
    7. 5.7  Switching Characteristics (1.65 V ≤ IOVDD ≤ 2 V)
    8. 5.8  Timing Requirements (2 V < IOVDD ≤ 5.5 V)
    9. 5.9  Switching Characteristics (2 V < IOVDD ≤ 5.5 V)
    10. 5.10 Timing Diagrams
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Internal Oscillator
        2. 7.3.3.2 External Clock
      4. 7.3.4 Modulator
      5. 7.3.5 Digital Filter
        1. 7.3.5.1 Wideband Filter
          1. 7.3.5.1.1 Wideband Filter Options
          2. 7.3.5.1.2 Sinc5 Filter Stage
          3. 7.3.5.1.3 FIR1 Filter Stage
          4. 7.3.5.1.4 FIR2 Filter Stage
          5. 7.3.5.1.5 FIR3 Filter Stage
          6. 7.3.5.1.6 FIR3 Default Coefficients
          7. 7.3.5.1.7 IIR Filter Stage
            1. 7.3.5.1.7.1 IIR Filter Stability
        2. 7.3.5.2 Low-Latency Filter (Sinc)
          1. 7.3.5.2.1 Sinc3 and Sinc4 Filters
          2. 7.3.5.2.2 Sinc3 + Sinc1 and Sinc4 + Sinc1 Cascade Filter
      6. 7.3.6 Power Supplies
        1. 7.3.6.1 AVDD1 and AVSS
        2. 7.3.6.2 AVDD2
        3. 7.3.6.3 IOVDD
        4. 7.3.6.4 Power-On Reset (POR)
        5. 7.3.6.5 CAPA and CAPD
      7. 7.3.7 VCM Output Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Speed Modes
      2. 7.4.2 Idle Mode
      3. 7.4.3 Standby Mode
      4. 7.4.4 Power-Down Mode
      5. 7.4.5 Reset
        1. 7.4.5.1 RESET Pin
        2. 7.4.5.2 Reset by SPI Register Write
        3. 7.4.5.3 Reset by SPI Input Pattern
      6. 7.4.6 Synchronization
        1. 7.4.6.1 Synchronized Control Mode
        2. 7.4.6.2 Start/Stop Control Mode
        3. 7.4.6.3 One-Shot Control Mode
      7. 7.4.7 Conversion-Start Delay Time
      8. 7.4.8 Calibration
        1. 7.4.8.1 OFFSET2, OFFSET1, OFFSET0 Calibration Registers (Addresses 0Ch, 0Dh, 0Eh)
        2. 7.4.8.2 GAIN2, GAIN1, GAIN0 Calibration Registers (Addresses 0Fh, 10h, 11h)
        3. 7.4.8.3 Calibration Procedure
    5. 7.5 Programming
      1. 7.5.1 Serial Interface (SPI)
        1. 7.5.1.1  Chip Select (CS)
        2. 7.5.1.2  Serial Clock (SCLK)
        3. 7.5.1.3  Serial Data Input (SDI)
        4. 7.5.1.4  Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.1.5  SPI Frame
        6. 7.5.1.6  Full-Duplex Operation
        7. 7.5.1.7  Device Commands
          1. 7.5.1.7.1 No-Operation
          2. 7.5.1.7.2 Read Register Command
          3. 7.5.1.7.3 Write Register Command
        8. 7.5.1.8  Read Conversion Data
          1. 7.5.1.8.1 Conversion Data
          2. 7.5.1.8.2 Data Ready
            1. 7.5.1.8.2.1 DRDY
            2. 7.5.1.8.2.2 SDO/DRDY
            3. 7.5.1.8.2.3 DRDY Bit
            4. 7.5.1.8.2.4 Clock Counting
          3. 7.5.1.8.3 STATUS Byte
        9. 7.5.1.9  Daisy-Chain Operation
        10. 7.5.1.10 3-Wire SPI Mode
          1. 7.5.1.10.1 3-Wire SPI Mode Frame Reset
        11. 7.5.1.11 SPI CRC
      2. 7.5.2 Register Memory CRC
        1. 7.5.2.1 Main Program Memory CRC
        2. 7.5.2.2 FIR Filter Coefficient CRC
        3. 7.5.2.3 IIR Filter Coefficient CRC
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 SPI Operation
      2. 9.1.2 Input Driver
      3. 9.1.3 Antialias Filter
      4. 9.1.4 Reference Voltage
      5. 9.1.5 Simultaneous-Sampling Systems
    2. 9.2 Typical Applications
      1. 9.2.1 A-Weighting Filter Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 PGA855 Programmable Gain Amplifier
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 THS4551 Antialias Filter Design
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Register Map

Table 8-1 shows the ADS127L21 register map. Register data are read or written one register byte at a time for each SPI operation. The FIR_BANK and IIR_BANK registers use a single address to read or write filter coefficients. Writing to any register address greater than the CONTROL register (address = 04h) results in a conversion restart and loss of synchronization. If conversions are stopped (START pin low or STOP bit written), conversions are not restarted after register writes.

Table 8-1 ADS127L21 Register Map Overview
ADDRESS REGISTER DEFAULT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
00h DEV_ID 02h DEV_ID[7:0]
01h REV_ID xxh REV_ID[7:0]
02h STATUS1 x1100xxxb CS_MODE ALV_FLAG POR_FLAG SPI_ERR CRC_ERR ADC_ERR MOD_FLAG DRDY
03h STATUS2 00h RESERVED I_CRC_ERR F_CRC_ERR M_CRC_ERR
04h CONTROL 00h RESET[5:0] START STOP
05h MUX 00h RESERVED MUX[1:0]
06h CONFIG1 00h DATA EXT_RNG REF_RNG INP_RNG VCM REFP_BUF AINP_BUF AINN_BUF
07h CONFIG2 08h RESERVED START_MODE[1:0] SPEED_MODE[1:0] STBY_MODE PWDN
08h CONFIG3 00h CLK_SEL CLK_DIV[1:0] OUT_DRV RESERVED SPI_CRC REG_CRC STATUS
09h FILTER1 00h FLTR_SEL[2:0] FLTR_OSR[4:0]
0Ah FILTER2 01h RESERVED DELAY[2:0] FLTR_SEQ FIR2_DIS FIR3_DIS IIR_DIS
0Bh FILTER3 01h RESERVED DATA_MODE[1:0]
0Ch OFFSET2 00h OFFSET[23:16]
0Dh OFFSET1 00h OFFSET[15:8]
0Eh OFFSET0 00h OFFSET[7:0]
0Fh GAIN2 40h GAIN[23:16]
10h GAIN1 00h GAIN[15:8]
11h GAIN0 00h GAIN[7:0]
12h MAIN_CRC 00h MAIN_CRC[7:0]
13h FIR_BANK xxh FIR_BANK[7:0]
14h FIR_CRC1 xxh FIR_CRC[15:8]
15h FIR_CRCx0 xxh FIR_CRC[7:0]
16h IIR_BANK xxh IIR_BANK[7:0]
17h IIR_CRC xxh IIR_CRC[7:0]

Table 8-2 lists the access codes of the registers.

Table 8-2 Register Access Codes
Access Type Code Description
Read R Read only
Write W Write only
Read and write R/W Read and write
Reset or default value -n Value after reset or the default value

DEV_ID Register (Address = 00h) [reset = 02h]

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Figure 8-1 DEV_ID Register
7 6 5 4 3 2 1 0
DEV_ID[7:0]
R-02h
Table 8-3 DEV_ID Register Field Descriptions
Bit Field Type Reset Description
7:0 DEV_ID[7:0] R 02h

Device ID.

02h = ADS127L21

REV_ID Register (Address = 01h) [reset = xxh]

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Figure 8-2 REV_ID Register
7 6 5 4 3 2 1 0
REVID[7:0]
R-xxxxxxxxb
Table 8-4 REV_ID Register Field Descriptions
Bit Field Type Reset Description
7:0 REV_ID[7:0] R xxxxxxxxb

Die revision ID.
The die revision ID can change during device production without notice.

STATUS1 Register (Address = 02h) [reset = x1100xxxb]

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Figure 8-3 STATUS1 Register
7 6 5 4 3 2 1 0
CS_MODE ALV_FLAG POR_FLAG SPI_ERR CRC_ERR ADC_ERR MOD_FLAG DRDY
R-xb R/W-1b R/W-1b R/W-0b R-0b R-xb R-xb R-xb
Table 8-5 STATUS1 Register Field Descriptions
Bit Field Type Reset Description
7 CS_MODE R xb

CS mode.
This bit indicates 4-wire or 3-wire SPI mode. The mode is determined by the state of CS at power up or after reset.
0b = 4-wire SPI operation (CS is active)
1b = 3-wire SPI operation (CS is tied low)
6 ALV_FLAG R/W 1b

Analog supply low-voltage flag.
This bit indicates a low-voltage was detected on the analog power supplies. Write 1b to clear the flag to detect the next low-voltage condition.
0b = No low-voltage detection from when the flag was last cleared
1b = Low-voltage detected
5 POR_FLAG R/W 1b

Power-on reset (POR) flag.
This bit indicates a reset at device power-on, by a brownout of the IOVDD supply, or by a user-initiated reset. Write 1b to clear the flag to detect the next reset.
0b = No reset from when the flag was last cleared
1b = Device reset occurred
4 SPI_ERR R/W 0b

SPI communication CRC error.
This bit indicates an SPI CRC error. If set, register write operations are blocked, except for the STATUS register that allows clearing the error (write 1b to clear the error). Register read operations remain functional. The SPI CRC error detection is enabled by the SPI_CRC bit of the CONFIG4 register.
0b = No SPI CRC error
1b = SPI CRC error
3 CRC_ERR R 0b

Global memory CRC error.
This bit is an OR of the main memory, the FIR coefficients, and the IIR coefficients CRC errors. If the values written to the associated CRC registers do not match the ADC calculation, individual error bits are set in the I_CRC_ERR, F_CRC_ERR, and M_CRC_ERR bits of the STATUS2 register. This flag auto-clears when the individual CRC errors are cleared. Set the REG_CRC bit of the CONFIG3 register to enable memory CRC error check.
0b = No global memory CRC error
1b = Global memory CRC error
2 ADC_ERR R xb

Internal ADC error.
ADC_ERR indicates an internal error. Perform a power cycle or reset the device.
0b = No ADC error
1b = ADC error
1 MOD_FLAG R xb

Modulator saturation flag.
This bit indicates modulator saturation occurred during the conversion cycle. The flag is valid at the end of the conversion cycle.
0b = No modulator saturation
1b = Modulator saturation during the conversion cycle
0 DRDY R xb

Data-ready bit.
This bit asserts when new conversion data are ready. The bit is the inverse of the DRDY pin. Poll this bit in lieu of the DRDY pin to determine if conversion data are new or are repeated data from the last read operation. In one-shot control mode, this bit remains at 1b until a new conversion is started.
0b = Data are not new
1b = Data are new

STATUS2 Register (Address = 03h) [reset = 00h]

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Figure 8-4 STATUS2 Register
7 6 5 4 3 2 1 0
RESERVED I_CRC_ERR F_CRC_ERR M_CRC_ERR
R-00000b R-0b R-0b R/W-0b
Table 8-6 STATUS2 Register Field Descriptions
Bit Field Type Reset Description
7:3 RESERVED R 00000b

Reserved
2 I_CRC_ERR R 0b

IIR coefficient memory CRC error.
If the value written to the IIR memory CRC register (register address 17h) does not match the internal calculation, the error is flagged to this bit and to the global CRC_ERR bit of the STATUS1 register. Clear the error by correcting the IIR_CRC register value and disable and re-enable the register CRC check (REG_CRC bit of the CONFIG3 register). Set the REG_CRC bit (CONFIG3 register) to enable the IIR memory error check.
0b = No IIR coefficient memory CRC error
1b = IIR coefficient memory CRC error
1 F_CRC_ERR R 0b

FIR coefficient memory CRC error.
If the value written to the FIR memory CRC register (register addresses 14h and 15h) do not match the internal calculation, the error is flagged to this bit and to the global CRC_ERR bit of the STATUS1 register. Clear the error by correcting the FIR_CRC register values and disable and re-enable the register CRC check (REG_CRC bit of the CONFIG3 register). Set the REG_CRC bit (CONFIG3 register) to enable the register bank error check.
0b = No FIR coefficient memory CRC error
1b = FIR coefficient memory CRC error
0 M_CRC_ERR R/W 0b

Main memory CRC error.
If the value written to the main register memory CRC register (register address 12h) does not match the internal calculation, the error is flagged to this bit and to the global CRC_ERR bit of the STATUS1 register. Clear the error by correcting the MAIN_CRC register value, then write 1b to this bit. Set the REG_CRC bit (CONFIG3 register) to enable the register bank error check.
0b = No main memory CRC error
1b = Main memory CRC error

CONTROL Register (Address = 04h) [reset = 00h]

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Figure 8-5 CONTROL Register
7 6 5 4 3 2 1 0
RESET[5:0] START STOP
W-000000b W-0b W-0b
Table 8-7 CONTROL Register Field Descriptions
Bit Field Type Reset Description
7:2 RESET[5:0] W 000000b

Device reset.
Write 010110b to reset the ADC. Set the adjacent START and STOP bits to 00b in the same write operation to reset the ADC. These bits always read 000000b.
1 START W 0b

Start conversion.
Conversions are started or restarted by writing 1b. In one-shot control mode, one conversion is started. In start/stop control mode, conversions are started and continue until stopped by the STOP bit. Writing 1b to the START bit while a conversion is ongoing restarts the conversion. This bit has no effect in synchronized control mode. Writing 1b to both the START and STOP bits has no effect. The START bit is self-clearing and always reads 0b.
0b = No operation
1b = Start or restart conversion
0 STOP W 0b

Stop conversion.
This bit stops conversions after the current conversion completes. This bit has no effect in synchronized control mode. Writing 1b to both the START and STOP has no effect. STOP is self-clearing and always reads 0b.
0b = No operation
1b = Stop conversion after the current conversion completes

MUX Register (Address = 05h) [reset = 00h]

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Figure 8-6 MUX Register
7 6 5 4 3 2 1 0
RESERVED MUX[1:0]
R-000000b R/W-00b
Table 8-8 MUX Register Field Descriptions
Bit Field Type Reset Description
7:2 RESERVED R 000000b Reserved
1:0 MUX[1:0] R/W 00b

Input multiplexer selection.

These bits select the polarity of the analog input and select the test modes. See the Analog Input section for details.
00b = Normal input polarity
01b = Inverted input polarity
10b = Offset and noise test: AINP and AINN disconnected, ADC inputs internally shorted to (AVDD1 + AVSS) / 2
11b = Common-mode test: ADC inputs internally shorted and connected to AINP

CONFIG1 Register (Address = 06h) [reset = 00h]

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Figure 8-7 CONFIG1 Register
7 6 5 4 3 2 1 0
DATA EXT_RNG REF_RNG INP_RNG VCM REFP_BUF AINP_BUF AINN_BUF
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 8-9 CONFIG1 Register Field Descriptions
Bit Field Type Reset Description
7 DATA R/W 0b Data resolution selection.
This bit selects the output data resolution.
0b = 24-bit resolution
1b = 16-bit resolution
6 EXT_RNG R/W 0b Extended input range selection.
This bit extends the input range by 25%. See the Input Range section for more details.
0b = Standard input range
1b = 25% extended input range
5 REF_RNG R/W 0b

Voltage reference range selection.
Program this bit to select the low- or high-reference voltage range to match the applied reference voltage. See the Recommended Operating Conditions table for the range of reference voltages. When the high-reference range is selected, the INP_RNG bit is internally overridden to the 1x input range.
0b = Low-reference range
1b = High-reference range
4 INP_RNG R/W 0b

Input range selection.
This bit selects the 1x or 2x input range. See the Input Range section for more details.
0b = 1x input range
1b = 2x input range
3 VCM R/W 0b

VCM output enable.
This bit enables the VCM output voltage pin. The VCM voltage is (AVDD1 + AVSS) / 2.
0b = Disabled
1b = Enabled
2 REFP_BUF R/W 0b

Reference positive buffer enable.
This bit enables the REFP reference input precharge buffer.
0b = Disabled
1b = Enabled
1 AINP_BUF R/W 0b

Analog input positive buffer enable.
This bit enables the AINP analog input precharge buffer.
0b = Disabled
1b = Enabled
0 AINN_BUF R/W 0b

Analog input negative buffer enable.
This bit enables the AINN analog input precharge buffer.
0b = Disabled
1b = Enabled

CONFIG2 Register (Address = 07h) [reset = 08h]

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Figure 8-8 CONFIG2 Register
7 6 5 4 3 2 1 0
RESERVED START_MODE[1:0] SPEED_MODE[1:0] STBY_MODE PWDN
R-0b R/W-00b R/W-10b R/W-0b R/W-0b
Table 8-10 CONFIG2 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 00b

Reserved
5:4 START_MODE[1:0] R/W 00b

START mode selection.
These bits program the mode of the START pin. See the Synchronization section for more details.
00b = Start/stop control mode
01b = One-shot control mode
10b = Synchronized control mode
11b = Reserved
3:2 SPEED_MODE[1:0] R/W 10b

Speed mode selection.
These bits program the speed modes of the device. The ADC clock frequency listed corresponds to the mode.
00b = Low-speed mode (fCLK = 3.2MHz)
01b = Mid-speed mode (fCLK = 12.8MHz)
10b = High-speed mode (fCLK = 25.6MHz)
11b = Max-speed mode (fCLK = 32.768MHz, external only)
1 STBY_MODE R/W 0b

Standby mode selection.
This bit enables the automatic standby mode when conversions are stopped.
0b = Idle mode; the ADC remains fully powered when conversions stop.
1b = Standby mode; the ADC powers down when conversions stop. Standby mode is exited when conversions restart.
0 PWDN R/W 0b

Power-down mode selection.
This bit powers down the ADC. All functions are powered down except for SPI operation and the digital LDO to retain user register settings.
0b = Normal operation
1b = Power-down mode

CONFIG3 Register (Address = 08h) [reset = 00h]

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Figure 8-9 CONFIG3 Register
7 6 5 4 3 2 1 0
CLK_SEL CLK_DIV[1:0] OUT_DRV RESERVED SPI_CRC REG_CRC STATUS
R/W-0b R/W-00b R/W-0b R-0b R/W-0b R/W-0b R/W-0b
Table 8-11 CONFIG3 Register Field Descriptions
Bit Field Type Reset Description
7 CLK_SEL R/W 0b

Clock selection.
Selects internal or external clock operation.
0b = Internal oscillator operation
1b = External clock operation
6:5 CLK_DIV[1:0] R/W 00b

Clock divider selection.
Select the clock division factor for either internal or external clock. Selecting the divide-by-2 and divide-by-16 clock division factors force the low-latency filter OSR values of the mid-speed mode to all other speed modes. See the FILTER1 register for a list of OSR values of the speed modes.
00b = fCLK / 1
01b = fCLK / 2
10b = fCLK / 8
11b = fCLK / 16
4 OUT_DRV R/W 0b

Digital output drive selection.
Select the drive strength of the digital outputs.
0b = Full-drive strength
1b = Half-drive strength
3 RESERVED R 0b Reserved
2 SPI_CRC R/W 0b

SPI CRC enable.
This bit enables the SPI CRC error detection. When enabled, the device verifies the CRC input byte and appends a CRC byte to the output data. The SPI_ERR bit of the STATUS byte sets if an input SPI CRC error is detected. Write 1b to the SPI_ERR bit to clear the error.
0b = Disabled
1b = Enabled
1 REG_CRC R/W 0b

Memory CRC enable.
This bit enables the main, IIR coefficient, and FIR coefficient memory CRC error check. If the values written to the associated CRC value registers do not match the ADC calculation, individual errors are reported to the I_CRC_ERR, F_CRC_ERR, and M_CRC_ERR error bits of the STATUS2 register. If any CRC error bit is set, the global CRC error bit (CRC_ERR) is set in the STATUS1 register. Toggle the REG_CRC bit to clear the I_CRC_ERR and F_CRC_ERR flags after correcting the CRC value.
0b = Disabled
1b = Enabled
0 STATUS R/W 0b

STATUS1 byte output enable.
Program this bit to prefix the STATUS1 register data to the conversion data. The STATUS1 register data are also prefixed to the register data output when reading registers.
0b = Disabled
1b = Enabled

FILTER1 Register (Address = 09h) [reset = 00h]

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Figure 8-10 FILTER1 Register
7 6 5 4 3 2 1 0
FLTR_SEL[2:0] FLTR_OSR[4:0]
R/W-000b R/W-00000b
Table 8-12 FILTER1 Register Field Descriptions
Bit Field Type Reset Description
7:5 FLTR_SEL[2:0] R/W 000b

Digital filter selection.
The function of these bits depend on the wideband or sinc filter mode selection made by the FLTR_OSR[4:0] bits.

If the wideband filter is selected by FLTR_OSR[4:0], these bits select the preset or programmable FIR filter coefficients.
000b = Preset FIR filter coefficients
001b to 110b = Reserved
111b = Programmable FIR filter coefficients

If the sinc filter is selected by FLTR_OSR[4:0], these bits select the sinc3 or sinc4 first stage filter.
000b = Sinc4 first stage filter
001b = Sinc3 first stage filter
010b to 111b = Reserved

4:0 FLTR_OSR[4:0] R/W 00000b

Digital filter mode and oversampling ratio selection.
These bits select the oversampling ratio and the filter mode (wideband or sinc). For sinc filter mode, sincx = sinc3 or sinc4 filter selection made by FLTR_SEL[2:0]. The wideband filter OSR values decrease by 2 if FIR2 or FIR3 is disabled, and decrease by 4 if FIR2 and FIR3 are disabled. The output data rate is equal to fMOD / OSR.
00000b = Wideband, OSR = 32
00001b = Wideband, OSR = 64
00010b = Wideband, OSR = 128
00011b = Wideband, OSR = 256
00100b = Wideband, OSR = 512
00101b = Wideband, OSR = 1024
00110b = Wideband, OSR = 2048
00111b = Wideband, OSR = 4096
01000b = Sincx, OSR = 12
01001b = Sincx, OSR = 16
01010b = Sincx, OSR = 24
01011b = Sincx, OSR = 32
01100b = Sincx, OSR = 64
01101b = Sincx, OSR = 128
01110b = Sincx, OSR = 256 (167 mid-speed mode)
01111b = Sincx, OSR = 333 (256 mid-speed mode)
10000b = Sincx, OSR = 512 (333 mid-speed mode)
10001b = Sincx, OSR = 667 (512 mid-speed mode)
10010b = Sincx, OSR = 1024 (667 mid-speed mode)
10011b = Sincx, OSR = 1333 (1024 mid-speed mode)
10100b = Sincx, OSR = 2048 (1333 mid-speed mode)
10101b = Sincx, OSR = 2667 (2048 mid-speed mode)
10110b = Sincx, OSR = 4096 (2667 mid-speed mode)
10111b = Sincx, OSR = 5333 (4096 mid-speed mode)
11000b = Sincx, OSR = 26667 (13333 mid-speed mode)
11001b = Sincx, OSR = 32000 (16000 mid-speed mode)
11010b = Sincx, OSR = 96000 (48000 mid-speed mode)
11011b = Sincx, OSR = 160000 (80000 mid-speed mode)
11100b = Sincx + sinc1, OSR = 26656 (13334 mid-speed mode)
11101b = Sincx + sinc1, OSR = 32000 (16000 mid-speed mode)
11110b = Sincx + sinc1, OSR = 96000 (48000 mid-speed mode
11111b = Sincx + sinc1, OSR = 160000 (80000 mid-speed mode)

FILTER2 Register (Address = 0Ah) [reset = 01h]

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Figure 8-11 FILTER2 Register
7 6 5 4 3 2 1 0
RESERVED DELAY[2:0] FLTR_SEQ FIR2_DIS FIR3_DIS IIR_DIS
R/W-0b R/W-000b R/W-0b R/W-0b R/W-0b R/W-1b
Table 8-13 FILTER2 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R 0b

Reserved
6:4 DELAY[2:0] R/W 000b

Conversion-start delay time selection.
These bits program a delay time between when the START pin is high or when writing to the START bit to the start of the first conversion (fMOD = fCLK / 2).
000b = 0
001b = 4 / fMOD
010b = 8 / fMOD
011b = 16 / fMOD
100b = 32 / fMOD
101b = 128 / fMOD
110b = 512 / fMOD
111b = 1024 / fMOD
3 FLTR_SEQ R/W 0b

Wideband filter computation sequence.
This bit programs the computational sequence of the IIR and FIR3 wideband filter sections.
0b = FIR3 then IIR
1b = IIR then FIR3
2 FIR2_DIS R/W 0b

Wideband filter, FIR2 section disable.
This bit disables the FIR2 section of the wideband filter.
0b = Enabled
1b = Disabled
1 FIR3_DIS R/W 0b

Wideband filter, FIR3 section disable.
This bit disables the FIR3 section of the wideband filter.
0b = Enabled
1b = Disabled
0 IIR_DIS R/W 1b

Wideband filter, IIR section disable.
This bit disables the IIR section of the wideband filter.
0b = Enabled
1b = Disabled

FILTER3 Register (Address = 0Bh) [reset = 01h]

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Figure 8-12 FILTER3 Register
7 6 5 4 3 2 1 0
RESERVED DATA_MODE[1:0]
R-000000b R/W-01b
Table 8-14 FILTER3 Register Field Descriptions
Bit Field Type Reset Description
7:2 Reserved[5:0] R 000000b

Reserved
1:0 DATA_MODE[1:0] R/W 01b

Data output pin function selection.
These bits program the function of the SDO/DRDY pin. For SPI daisy-chain connection, use the data-output only mode.
00b = SDO/DRDY pin is data-output only mode
01b = SDO/DRDY is a dual mode: Data output and data ready
10b = Same as mode 01b, except SDO/DRDY is active when CS is high
11b = Reserved

OFFSET2, OFFSET1, OFFSET0 Registers (Addresses = 0Ch, 0Dh, 0Eh) [reset = 00h, 00h, 00h]

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Figure 8-13 OFFSET2, OFFSET1, OFFSET0 Registers
7 6 5 4 3 2 1 0
OFFSET[23:16]
R/W-00000000b
7 6 5 4 3 2 1 0
OFFSET[15:8]
R/W-00000000b
7 6 5 4 3 2 1 0
OFFSET[7:0]
R/W-00000000b
Table 8-15 OFFSET Registers Field Description
Bit Field Type Reset Description
23:0 OFFSET[23:0] R/W 000000h

User offset calibration value.
Three registers form the 24-bit offset calibration word. OFFSET[23:0] is in two's-complement representation and is subtracted from the conversion result. The offset operation precedes the gain operation.

GAIN2, GAIN1, GAIN0 Registers (Addresses = 0Fh, 10h, 11h) [reset = 40h, 00h, 00h]

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Figure 8-14 GAIN2, GAIN1, GAIN0 Registers
7 6 5 4 3 2 1 0
GAIN[23:16]
R/W-01000000b
7 6 5 4 3 2 1 0
GAIN[15:8]
R/W-00000000b
7 6 5 4 3 2 1 0
GAIN[7:0]
R/W-00000000b
Table 8-16 GAIN Registers Field Description
Bit Field Type Reset Description
23:0 GAIN[23:0] R/W 400000h

User gain calibration value.
Three registers form the 24-bit gain calibration word. GAIN[23:0] is a straight binary representation and normalized to 400000h for gain = 1. The conversion data are multiplied by GAIN[23:0] / 400000h after the offset operation.

MAIN_CRC Register (Address = 12h) [reset = 00h]

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Figure 8-15 MAIN_CRC Register
7 6 5 4 3 2 1 0
MAIN_CRC[7:0]
R/W-00000000b
Table 8-17 MAIN_CRC Register Field Descriptions
Bit Field Type Reset Description
7:0 MAIN_CRC[7:0] R/W 00h

Main memory CRC value.
The main memory CRC is computed over registers 0h and 1h, skipping registers 2h, 3h, and 4h, and continuing with registers 5h through 11h. Write the computed CRC value to this register. If the value does not match the internal calculation, the M_REG_ERR bit is set in the STATUS2 register. The global CRC_ERR bit is also set in the STATUS1 register. Set the REG_CRC bit of the CONFIG3 register to enable all three types of memory CRC.

FIR_BANK Register (Address = 13h) [reset = xxh]

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Figure 8-16 FIR_BANK Register
7 6 5 4 3 2 1 0
FIR_BANK[7:0]
R/W-xxh
Table 8-18 FIR_BANK Register Field Descriptions
Bit Field Type Reset Description
7:0 FIR_BANK[7:0] R/W xxh

FIR programmable filter coefficient register memory bank
This register is a single address space that stores the 128 coefficients of the programmable FIR filter memory. Perform sequential read and write operations to the same register address to increment an internal pointer to the next memory location. Any change of address to another register in a read or write operation resets the internal pointer to the first memory space. The reset values of the programmable coefficients are undefined. See the FIR3 Filter Stage section for the FIR coefficient byte sequence.

FIR_CRC1, FIR_CRC0 Registers (Addresses = 14h, 15h) [reset = xxh, xxh]

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Figure 8-17 FIR_CRC1, FIR_CRC0 Registers
7 6 5 4 3 2 1 0
FIR_CRC1[15:8]
R/W-xxh
7 6 5 4 3 2 1 0
FIR_CRC0[7:0]
R/W-xxh
Table 8-19 FIR_CRC1, FIR_CRC0 Registers Field Description
Bit Field Type Reset Description
23:0 FIR_CRC[23:0] R/W xxxxh

Programmable FIR filter coefficients CRC value.
The programmable FIR filter coefficients CRC is a user-computed value for the 128, 32-bit FIR filter coefficients. A 16-bit polynomial is used for the FIR coefficient CRC (x16 + x15 + x2 + 1). FIR_CRC1 is the high byte value. If the value written does not match an internal calculation, the F_REG_ERR bit is set in the STATUS2 register. The global CRC_ERR bit is also set in the STATUS1 register. Set the REG_CRC bit of the CONFIG3 register to enable all three types of memory bank CRC. See the FIR Filter Coefficient CRC section for more details.

IIR_BANK Register (Address = 16h) [reset = xxh]

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Figure 8-18 IIR_BANK Register
7 6 5 4 3 2 1 0
IIR_BANK[7:0]
R/W-xxh
Table 8-20 IIR_BANK Register Field Descriptions
Bit Field Type Reset Description
7:0 IIR_BANK[7:0] R/W xxh

IIR programmable filter coefficients register bank.
This register is a single address space that stores the programmable coefficients for the IIR filter. Successive read and write operations to this register increment an internal pointer to the next memory byte location. See Table 7-8 for the byte sequence of the IIR filter coefficients. Any change of address to another resister during a read or write operation resets the operation to the first IIR coefficient memory location.

IIR_CRC Register (Address = 17h) [reset = xxh]

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Figure 8-19 IIR_CRC Register
7 6 5 4 3 2 1 0
IIR_CRC[7:0]
R/W-xxh
Table 8-21 IIR_CRC Register Field Descriptions
Bit Field Type Reset Description
7:0 IIR_CRC[7:0] R/W xxh

IIR filter coefficients memory CRC value.
The IIR filter coefficients memory CRC is a user-computed value of the entire IIR filter memory. If the value written does not match an internal calculation, the I_REG_ERR bit is set in the STATUS2 register. The global CRC_ERR bit is also set in the STATUS1 register. Set the REG_CRC bit of the CONFIG3 register to enable all three types of memory bank CRC. See the IIR Filter Coefficient CRC section for more details.