SBASAK4B March 2023 – April 2024 ADS127L21
PRODUCTION DATA
In 3-wire SPI mode, unintended SCLK transitions potentially misaligns the frame, resulting in loss of SPI synchronization. As shown in Figure 7-46, the SPI is resynchronized by sending an SPI reset pattern. The reset pattern is a minimum of 63 consecutive 1s followed by one 0 at the 64th SCLK. The 65th SCLK starts a new SPI frame. Optionally, completely reset the ADC by toggling RESET or by the reset pattern described in the Reset by SPI Input PatternReset by SPI Input PatternReset by SPI Input Pattern section.