SBASAK4B March   2023  – April 2024 ADS127L21

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements (1.65 V ≤ IOVDD ≤ 2 V)
    7. 5.7  Switching Characteristics (1.65 V ≤ IOVDD ≤ 2 V)
    8. 5.8  Timing Requirements (2 V < IOVDD ≤ 5.5 V)
    9. 5.9  Switching Characteristics (2 V < IOVDD ≤ 5.5 V)
    10. 5.10 Timing Diagrams
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Internal Oscillator
        2. 7.3.3.2 External Clock
      4. 7.3.4 Modulator
      5. 7.3.5 Digital Filter
        1. 7.3.5.1 Wideband Filter
          1. 7.3.5.1.1 Wideband Filter Options
          2. 7.3.5.1.2 Sinc5 Filter Stage
          3. 7.3.5.1.3 FIR1 Filter Stage
          4. 7.3.5.1.4 FIR2 Filter Stage
          5. 7.3.5.1.5 FIR3 Filter Stage
          6. 7.3.5.1.6 FIR3 Default Coefficients
          7. 7.3.5.1.7 IIR Filter Stage
            1. 7.3.5.1.7.1 IIR Filter Stability
        2. 7.3.5.2 Low-Latency Filter (Sinc)
          1. 7.3.5.2.1 Sinc3 and Sinc4 Filters
          2. 7.3.5.2.2 Sinc3 + Sinc1 and Sinc4 + Sinc1 Cascade Filter
      6. 7.3.6 Power Supplies
        1. 7.3.6.1 AVDD1 and AVSS
        2. 7.3.6.2 AVDD2
        3. 7.3.6.3 IOVDD
        4. 7.3.6.4 Power-On Reset (POR)
        5. 7.3.6.5 CAPA and CAPD
      7. 7.3.7 VCM Output Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Speed Modes
      2. 7.4.2 Idle Mode
      3. 7.4.3 Standby Mode
      4. 7.4.4 Power-Down Mode
      5. 7.4.5 Reset
        1. 7.4.5.1 RESET Pin
        2. 7.4.5.2 Reset by SPI Register Write
        3. 7.4.5.3 Reset by SPI Input Pattern
      6. 7.4.6 Synchronization
        1. 7.4.6.1 Synchronized Control Mode
        2. 7.4.6.2 Start/Stop Control Mode
        3. 7.4.6.3 One-Shot Control Mode
      7. 7.4.7 Conversion-Start Delay Time
      8. 7.4.8 Calibration
        1. 7.4.8.1 OFFSET2, OFFSET1, OFFSET0 Calibration Registers (Addresses 0Ch, 0Dh, 0Eh)
        2. 7.4.8.2 GAIN2, GAIN1, GAIN0 Calibration Registers (Addresses 0Fh, 10h, 11h)
        3. 7.4.8.3 Calibration Procedure
    5. 7.5 Programming
      1. 7.5.1 Serial Interface (SPI)
        1. 7.5.1.1  Chip Select (CS)
        2. 7.5.1.2  Serial Clock (SCLK)
        3. 7.5.1.3  Serial Data Input (SDI)
        4. 7.5.1.4  Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.1.5  SPI Frame
        6. 7.5.1.6  Full-Duplex Operation
        7. 7.5.1.7  Device Commands
          1. 7.5.1.7.1 No-Operation
          2. 7.5.1.7.2 Read Register Command
          3. 7.5.1.7.3 Write Register Command
        8. 7.5.1.8  Read Conversion Data
          1. 7.5.1.8.1 Conversion Data
          2. 7.5.1.8.2 Data Ready
            1. 7.5.1.8.2.1 DRDY
            2. 7.5.1.8.2.2 SDO/DRDY
            3. 7.5.1.8.2.3 DRDY Bit
            4. 7.5.1.8.2.4 Clock Counting
          3. 7.5.1.8.3 STATUS Byte
        9. 7.5.1.9  Daisy-Chain Operation
        10. 7.5.1.10 3-Wire SPI Mode
          1. 7.5.1.10.1 3-Wire SPI Mode Frame Reset
        11. 7.5.1.11 SPI CRC
      2. 7.5.2 Register Memory CRC
        1. 7.5.2.1 Main Program Memory CRC
        2. 7.5.2.2 FIR Filter Coefficient CRC
        3. 7.5.2.3 IIR Filter Coefficient CRC
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 SPI Operation
      2. 9.1.2 Input Driver
      3. 9.1.3 Antialias Filter
      4. 9.1.4 Reference Voltage
      5. 9.1.5 Simultaneous-Sampling Systems
    2. 9.2 Typical Applications
      1. 9.2.1 A-Weighting Filter Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 PGA855 Programmable Gain Amplifier
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 THS4551 Antialias Filter Design
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.3.5.2.1 Sinc3 and Sinc4 Filters

The sinc filter averages and decimates the high-speed modulator data to produce high-resolution output data at reduced data rate. Increasing the OSR value decreases the data rate and simultaneously reduces signal bandwidth and conversion noise resulting from increased decimation and data averaging. Table 7-14 lists the sinc3 and sinc4 filter –3dB frequency and latency time.

Table 7-9 Sinc3 and Sinc4 Filter Characteristics
MODE fCLK
(MHz)		 OSR DATA RATE
(kSPS)		 –3dB FREQUENCY (kHz) LATENCY TIME(1) (μs)
SINC3 SINC4 SINC3 SINC4
Max speed 32.768 12 1365.3 357.0 310.2 2.97 3.66
High speed 25.6 1066.6 278.9 242.3 3.73 4.69
Mid speed 12.8 533.3 139.5 121.2 7.46 9.36
Low speed 3.2 133.33 34.9 30.3 29.8 37.4
Max speed 32.768 16 1024 267.8 232.7 3.66 4.63
High speed 25.6 800 209.2 181.8 4.67 5.95
Mid speed 12.8 400 104.6 90.9 9.33 11.9
Low speed 3.2 100 26.2 22.7 37.4 47.3
Max speed 32.768 24 682.67 178.5 155.1 5.12 6.64
High speed 25.6 533.3 139.5 121.2 6.57 8.43
Mid speed 12.8 266.67 69.7 60.6 13.1 16.9
Low speed 3.2 66.67 17.4 15.1 52.3 67.4
Max speed 32.768 32 512 133.9 116.3 6.59 8.55
High speed 25.6 400 104.6 90.9 8.42 10.9
Mid speed 12.8 200 52.3 45.4 16.9 21.8
Low speed 3.2 50 13.1 11.4 67.3 87.2
Max speed 32.768 64 256 66.9 58.2 12.4 16.4
High speed 25.6 200 52.3 45.4 16.0 21.0
Mid speed 12.8 100 26.2 22.7 31.8 41.9
Low speed 3.2 25 6.54 5.68 127 167
Max speed 32.768 128 128 33.5 29.1 24.2 32.0
High speed 25.6 100 26.2 22.7 31.0 41.0
Mid speed 12.8 50 13.1 11.4 61.9 81.9
Low speed 3.2 12.5 3.27 2.84 247 327
Mid speed 12.8 167 38.323 10.0 8.71 80.2 106
Max speed 32.768 256 64 16.7 14.5 47.6 63.2
High speed 25.6 50 13.1 11.4 60.9 80.9
Mid speed 12.8 25 6.54 5.68 121.9 162
Low speed 3.2 6.25 1.63 1.42 487 648
Max speed 32.768 333 49.201 12.9 11.2 61.7 82.0
High speed 25.6 38.438 10.1 8.73 79.0 105
Mid speed 12.8 19.219 5.03 4.37 158 210
Low speed 3.2 4.804 1.26 1.09 631 840
Max speed 32.768 512 32 8.37 7.27 94.5 126
High speed 25.6 25 6.54 5.68 121 161
Mid speed 12.8 12.5 3.27 2.84 242 322
Low speed 3.2 3.125 0.817 0.710 967 1287
Max speed 32.768 667 24.564 6.42 5.58 123 164
High speed 25.6 19.19 5.02 4.36 157 209
Mid speed 12.8 9.595 2.51 2.18 314 419
Low speed 3.2 2.39 0.627 0.545 1258 1675
Max speed 32.768 1024 16 4.18 3.64 188 251
High speed 25.6 12.5 3.27 2.84 241 321
Mid speed 12.8 6.25 1.63 1.42 482 642
Low speed 3.2 1.5625 0.409 0.355 1927 2567
Max speed 32.768 1333 12.291 3.21 2.79 245 326
High speed 25.6 9.602 2.51 2.18 313 417
Mid speed 12.8 4.801 1.26 1.09 627 835
Low speed 3.2 1.2 0.314 0.273 2507 3340
Max speed 32.768 2048 8 2.09 1.82 376 501
High speed 25.6 6.25 1.63 1.42 481 641
Mid speed 12.8 3.125 0.817 0.710 962 1282
Low speed 3.2 0.7813 0.204 0.178 3847 5127
Max speed 32.768 2667 6.143 1.61 1.40 489 652
High speed 25.6 4.799 1.26 1.09 626 834
Mid speed 12.8 2.4 0.628 0.545 1252 1669
Low speed 3.2 0.6 0.157 0.136 5008 6675
Max speed 32.768 4096 4 1.046 0.909 751 1001
High speed 25.6 3.125 0.817 0.710 961 1281
Mid speed 12.8 1.563 0.409 0.355 1922 2562
Low speed 3.2 0.391 0.102 0.089 7687 10247
Max speed 32.768 5333 3.072 0.803 0.698 977 1303
High speed 25.6 2.4 0.628 0.545 1251 1667
Low speed 3.2 0.3 0.078 0.068 10006 13340
Mid speed 12.8 13333 0.480 0.126 0.109 6251 8335
Mid speed 12.8 16000 0.400 0.105 0.0909 7501 10002
Max speed 32.768 26667 0.614 0.161 0.140 4884 6511
High speed 25.6 0.480 0.126 0.109 6251 8334
Low speed 3.2 0.06 0.0157 0.0136 50008 66675
Max speed 32.768 32000 0.512 0.134 0.116 5860 7813
High speed 25.6 0.4 0.105 0.091 7501 10001
Low speed 3.2 0.05 0.0131 0.0114 60007 80007
Mid speed 12.8 48000 0.133 0.0349 0.0303 22502 30002
Mid speed 12.8 80000 0.08 0.0209 0.0182 37502 50002
Max speed 32.768 96000 0.17067 0.0446 0.0388 17579 23438
High speed 25.6 0.133 0.0349 0.0303 22501 30001
Low speed 3.2 0.0166 0.0044 0.0038 180007 240007
Max speed 32.768 160000 0.102 0.0268 0.0233 29298 39063
High speed 25.6 0.08 0.0209 0.0182 37501 50001
Low speed 3.2 0.01 0.0026 0.0023 300005 400004
(1) Latency time increases by 8 / fCLK (μs) when analog input buffers are enabled.

Because of the reduction of data averaging performed in the filtering process, the full 24 bits of output data are not available for OSR ≤ 24. Table 7-10 summarizes output resolution for OSR values ≤ 24.

Table 7-10 Sinc3 and Sinc4 Data Resolution
OSR RESOLUTION (Bits)
12 19
16 20.5
24 23

Figure 7-24 and Figure 7-25 show the sinc filter frequency response. The frequency response consists of a series of response nulls occurring at fDATA and multiples thereof. At the null frequencies, the filter has zero gain. Figure 7-25 shows the folding of the frequency response starting at the fMOD / 2 frequency. No attenuation is provided by the filter at input frequencies near n · fMOD (n = 1, 2, 3, and so on).

GUID-20230623-SS0I-6NKC-5W8W-ZF2L2BS8JFQ6-low.svgFigure 7-24 Sinc3 and Sinc4 Frequency Response
(OSR = 32)
GUID-FCD4D1BC-65D8-4C46-AC26-E509568F7D47-low.gifFigure 7-25 Sinc4 Frequency Response to fMOD (OSR = 32)

Table 7-11 shows the normal-mode rejection of the filter for data rates equal to common line-cycle frequencies.

Table 7-11 Normal-Mode Rejection
MODE OSR fDATA (SPS) 2% CLOCK VARIATION 6% CLOCK VARIATION
SINC3 FILTER SINC4 FILTER SINC3 FILTER SINC4 FILTER
Low-speed 96000 16.6 100 dB 135 dB 72 dB 95 dB
Low-speed 32000 50
Low-speed 26667 60
High-speed 32000 400