SBASAK4B March   2023  – April 2024 ADS127L21

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements (1.65 V ≤ IOVDD ≤ 2 V)
    7. 5.7  Switching Characteristics (1.65 V ≤ IOVDD ≤ 2 V)
    8. 5.8  Timing Requirements (2 V < IOVDD ≤ 5.5 V)
    9. 5.9  Switching Characteristics (2 V < IOVDD ≤ 5.5 V)
    10. 5.10 Timing Diagrams
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Internal Oscillator
        2. 7.3.3.2 External Clock
      4. 7.3.4 Modulator
      5. 7.3.5 Digital Filter
        1. 7.3.5.1 Wideband Filter
          1. 7.3.5.1.1 Wideband Filter Options
          2. 7.3.5.1.2 Sinc5 Filter Stage
          3. 7.3.5.1.3 FIR1 Filter Stage
          4. 7.3.5.1.4 FIR2 Filter Stage
          5. 7.3.5.1.5 FIR3 Filter Stage
          6. 7.3.5.1.6 FIR3 Default Coefficients
          7. 7.3.5.1.7 IIR Filter Stage
            1. 7.3.5.1.7.1 IIR Filter Stability
        2. 7.3.5.2 Low-Latency Filter (Sinc)
          1. 7.3.5.2.1 Sinc3 and Sinc4 Filters
          2. 7.3.5.2.2 Sinc3 + Sinc1 and Sinc4 + Sinc1 Cascade Filter
      6. 7.3.6 Power Supplies
        1. 7.3.6.1 AVDD1 and AVSS
        2. 7.3.6.2 AVDD2
        3. 7.3.6.3 IOVDD
        4. 7.3.6.4 Power-On Reset (POR)
        5. 7.3.6.5 CAPA and CAPD
      7. 7.3.7 VCM Output Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Speed Modes
      2. 7.4.2 Idle Mode
      3. 7.4.3 Standby Mode
      4. 7.4.4 Power-Down Mode
      5. 7.4.5 Reset
        1. 7.4.5.1 RESET Pin
        2. 7.4.5.2 Reset by SPI Register Write
        3. 7.4.5.3 Reset by SPI Input Pattern
      6. 7.4.6 Synchronization
        1. 7.4.6.1 Synchronized Control Mode
        2. 7.4.6.2 Start/Stop Control Mode
        3. 7.4.6.3 One-Shot Control Mode
      7. 7.4.7 Conversion-Start Delay Time
      8. 7.4.8 Calibration
        1. 7.4.8.1 OFFSET2, OFFSET1, OFFSET0 Calibration Registers (Addresses 0Ch, 0Dh, 0Eh)
        2. 7.4.8.2 GAIN2, GAIN1, GAIN0 Calibration Registers (Addresses 0Fh, 10h, 11h)
        3. 7.4.8.3 Calibration Procedure
    5. 7.5 Programming
      1. 7.5.1 Serial Interface (SPI)
        1. 7.5.1.1  Chip Select (CS)
        2. 7.5.1.2  Serial Clock (SCLK)
        3. 7.5.1.3  Serial Data Input (SDI)
        4. 7.5.1.4  Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.1.5  SPI Frame
        6. 7.5.1.6  Full-Duplex Operation
        7. 7.5.1.7  Device Commands
          1. 7.5.1.7.1 No-Operation
          2. 7.5.1.7.2 Read Register Command
          3. 7.5.1.7.3 Write Register Command
        8. 7.5.1.8  Read Conversion Data
          1. 7.5.1.8.1 Conversion Data
          2. 7.5.1.8.2 Data Ready
            1. 7.5.1.8.2.1 DRDY
            2. 7.5.1.8.2.2 SDO/DRDY
            3. 7.5.1.8.2.3 DRDY Bit
            4. 7.5.1.8.2.4 Clock Counting
          3. 7.5.1.8.3 STATUS Byte
        9. 7.5.1.9  Daisy-Chain Operation
        10. 7.5.1.10 3-Wire SPI Mode
          1. 7.5.1.10.1 3-Wire SPI Mode Frame Reset
        11. 7.5.1.11 SPI CRC
      2. 7.5.2 Register Memory CRC
        1. 7.5.2.1 Main Program Memory CRC
        2. 7.5.2.2 FIR Filter Coefficient CRC
        3. 7.5.2.3 IIR Filter Coefficient CRC
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 SPI Operation
      2. 9.1.2 Input Driver
      3. 9.1.3 Antialias Filter
      4. 9.1.4 Reference Voltage
      5. 9.1.5 Simultaneous-Sampling Systems
    2. 9.2 Typical Applications
      1. 9.2.1 A-Weighting Filter Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 PGA855 Programmable Gain Amplifier
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 THS4551 Antialias Filter Design
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.3.5.1.1 Wideband Filter Options

The wideband filter provides inter-stage bypassing and the option of reversing the FIR3-IIR filter sequence. Figure 7-10 shows the wideband filter options. Disabling a filter stage bypasses the filter function and associated decimation. For example, with the FIR2, FIR3, and IIR filter stages disabled, FIR1 filter data are output at four times the normal data rate. There are no restrictions to the number of filter options. However, if FIR2 is disabled, then disable the FIR3 and IIR filters for an overall OSR of 16.

GUID-20221219-SS0I-SXRG-W0JB-QJPXZK3WFBB8-low.svg Figure 7-10 Wideband Filter Options