SBAS559A May   2022  – December 2022 ADS1285

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: 1.65 V ≤ IOVDD ≤ 1.95 V and 2.7 V ≤ IOVDD ≤ 3.6 V
    7. 6.7 Switching Characteristics: 1.65V ≤ IOVDD ≤ 1.95V and 2.7 V ≤ IOVDD ≤ 3.6 V
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
      2. 8.3.2 PGA and Buffer
        1. 8.3.2.1 Programmable Gain Amplifier (PGA)
        2. 8.3.2.2 Buffer Operation (PGA Bypass)
      3. 8.3.3 Voltage Reference Input
      4. 8.3.4 IOVDD Power Supply
      5. 8.3.5 Modulator
        1. 8.3.5.1 Modulator Overdrive
      6. 8.3.6 Digital Filter
        1. 8.3.6.1 Sinc Filter Section
        2. 8.3.6.2 FIR Filter Section
        3. 8.3.6.3 Group Delay and Step Response
          1. 8.3.6.3.1 Linear Phase Response
          2. 8.3.6.3.2 Minimum Phase Response
        4. 8.3.6.4 HPF Stage
      7. 8.3.7 Clock Input
      8. 8.3.8 GPIO
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
      2. 8.4.2 Power-Down Mode
      3. 8.4.3 Reset
      4. 8.4.4 Synchronization
        1. 8.4.4.1 Pulse-Sync Mode
        2. 8.4.4.2 Continuous-Sync Mode
      5. 8.4.5 Sample Rate Converter
      6. 8.4.6 Offset and Gain Calibration
        1. 8.4.6.1 OFFSET Register
        2. 8.4.6.2 GAIN Register
        3. 8.4.6.3 Calibration Procedure
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Input (DIN)
        4. 8.5.1.4 Data Output (DOUT)
        5. 8.5.1.5 Data Ready (DRDY)
      2. 8.5.2 Conversion Data Format
      3. 8.5.3 Commands
        1. 8.5.3.1  Single Byte Command
        2. 8.5.3.2  WAKEUP: Wake Command
        3. 8.5.3.3  STANDBY: Software Power-Down Command
        4. 8.5.3.4  SYNC: Synchronize Command
        5. 8.5.3.5  RESET: Reset Command
        6. 8.5.3.6  Read Data Direct
        7. 8.5.3.7  RDATA: Read Conversion Data Command
        8. 8.5.3.8  RREG: Read Register Command
        9. 8.5.3.9  WREG: Write Register Command
        10. 8.5.3.10 OFSCAL: Offset Calibration Command
        11. 8.5.3.11 GANCAL: Gain Calibration Command
    6. 8.6 Register Map
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1 ID/SYNC: Device ID, SYNC Register (Address = 00h) [Reset = xxxx0000b]
        2. 8.6.1.2 CONFIG0: Configuration Register 0 (Address = 01h) [Reset = 12h]
        3. 8.6.1.3 CONFIG1: Configuration Register 1 (Address = 02h) [Reset = 00h]
        4. 8.6.1.4 HPF0, HPF1: High-Pass Filter Registers (Address = 03h, 04h) [Reset = 32h, 03h]
        5. 8.6.1.5 OFFSET0, OFFSET1, OFFSET2: Offset Calibration Registers (Address = 05h, 06h, 07h) [Reset = 00h, 00h, 00h]
        6. 8.6.1.6 GAIN0, GAIN1, GAIN2: Gain Calibration Registers (Address = 08h, 09h, 0Ah) [Reset = 00h, 00h, 40h]
        7. 8.6.1.7 GPIO: Digital Input/Output Register (Address = 0Bh) [Reset = 000xx000b]
        8. 8.6.1.8 SRC0, SRC1: Sample Rate Converter Registers (Address = 0Ch, 0Dh) [Reset = 00h, 80h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Analog Power Supplies
      2. 9.3.2 Digital Power Supply
      3. 9.3.3 Grounds
      4. 9.3.4 Thermal Pad
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Power supply voltages AVDD1 to AVSS –0.3 5.5 V
AVSS to AGND –2.8 0.3
AVDD2 to AGND –0.3 5.5
AVDD2 to AVSS –0.3 5.5
IOVDD to DGND –0.3 3.9
IOVDD to DGND (IOVDD connected to CAPD) –0.3 2.2
Grounds AGND to DGND – 0.3  0.3 V
Analog input voltage AIN1P, AIN1N, AIN2P, AIN2N, REFP, REFN AVSS – 0.3 AVDD1 + 0.3 V

Digital input voltage

 CLK, DIN, SCLK, CS, GPIO0, GPIO1, SYNC, RESET, PWDN DGND – 0.3 IOVDD + 0.3 V
Input current Continuous, any digital or analog pin (2) –10 10 mA
Temperature Junction, TJ 150 °C
Storage, Tstg –60 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional – this may affect device reliability, functionality, performance, and shorten the device
lifetime.
(2) Analog input pins AIN1P, AIN1N, AIN2P, AIN2N, REFP and REFN are diode-clamped to AVDD1 and AVSS. Limit the input current to 10 mA in the event the analog input voltage exceeds AVDD1 + 0.3 V or AVSS – 0.3 V. Digital input pins are clamped to IOVDD and DGND. Limit the input current if the digital input voltage exceeds IOVDD + 0.3 V or DGND – 0.3 V.