SNAS602C FEBRUARY   2013  – December 2014 ADS1293

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Application Diagram
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Write Timing Requirements
    7. 7.7 Read Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Flexible Routing Switch
      2. 8.3.2  Battery Monitoring
      3. 8.3.3  Test Mode
      4. 8.3.4  Analog Front-End
      5. 8.3.5  Instrumentation Amplifier (INA)
        1. 8.3.5.1 Instrumentation Amplifier Fault Detection
      6. 8.3.6  Sigma-Delta Modulator (SDM)
        1. 8.3.6.1 Sigma-Delta Modulator Fault Detection
      7. 8.3.7  Programmable Digital Filters
      8. 8.3.8  Filter Settling Time
      9. 8.3.9  Analog Pace Channel
      10. 8.3.10 Wilson Reference
        1. 8.3.10.1 Wilson Central Terminal
        2. 8.3.10.2 Goldberger Terminals
      11. 8.3.11 Common-Mode (CM) Detector
        1. 8.3.11.1 Cable Shield Driving
        2. 8.3.11.2 Common-Mode Output Range (CMOR)
      12. 8.3.12 Right-Leg Drive (RLD)
      13. 8.3.13 Capacitive Load Driving
      14. 8.3.14 Error Status: RLD Rail
      15. 8.3.15 Lead-Off Detection (LOD)
      16. 8.3.16 DC Lead-Off Detect
      17. 8.3.17 Analog AC Lead-Off Detect
      18. 8.3.18 Digital AC Lead-Off Detect
      19. 8.3.19 Clock Oscillator
      20. 8.3.20 Synchronization
      21. 8.3.21 Single-Chip Multi-Channel Synchronization
      22. 8.3.22 Multichip Synchronization
      23. 8.3.23 Synchronization Errors
      24. 8.3.24 Alarm Functions
      25. 8.3.25 Error Filtering
      26. 8.3.26 ALARMB Pin and Error Masking
      27. 8.3.27 Error Register Automatic Clearing Description
      28. 8.3.28 Alarm Propagation
      29. 8.3.29 Reference Voltage Generators
      30. 8.3.30 Power Management
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Sampling Rate
      2. 8.4.2 High Sampling Rate
      3. 8.4.3 Ouput Code (ADCOUT)
    5. 8.5 Programming
      1. 8.5.1 Serial Digital Interface
      2. 8.5.2 Digital Output Drive Strength
      3. 8.5.3 SPI Protocol
      4. 8.5.4 Random Register Access Protocol
      5. 8.5.5 Auto-Incrementing Address
      6. 8.5.6 Streaming
      7. 8.5.7 Data Ready Bar
      8. 8.5.8 Simultaneous ECG and Pace Data Read
    6. 8.6 Register Maps
      1. 8.6.1  Operation Mode Registers
      2. 8.6.2  Input Channel Selection Registers
      3. 8.6.3  Lead-Off Detect Control Registers
      4. 8.6.4  Common-Mode Detection and Right-Leg Drive Common-Mode Feedback Control Registers
      5. 8.6.5  Wilson Control Registers
      6. 8.6.6  Reference Registers
      7. 8.6.7  OSC Control Registers
      8. 8.6.8  AFE Control Registers
      9. 8.6.9  Error Status Registers
      10. 8.6.10 Digital Registers
      11. 8.6.11 Pace and ECG Data Read Back Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 3-Lead ECG Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 5-Lead ECG Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 8- or 12-Lead ECG Application
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Power Supply Recommendations

TI recommends placing a 0.1-µF ceramic bypass capacitor from VDD to ground as close as possible to the pin. An electrolytic or tantalum capacitor of value larger than 1 µF is recommeded as a bulk capacitor. The bulk capacitor does not need to be in close proximity to the device and could be close to the voltage source terminals or at the output of the voltage regulator. The same recommendations apply for the VDDIO pin.

The CVREF pin requires a 1-µF bypass capacitor-to-ground; this capacitor should have a low ESR and should be placed as close as possible to the pin. The RLDREF pin requires a 0.1-µF ceramic bypass capacitor-to-ground; this capacitor should be placed as close as possible to the pin.