SBAS590E March   2016  – June 2020 ADS131A02 , ADS131A04

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: Asynchronous Interrupt Interface Mode
    7. 7.7  Switching Characteristics: Asynchronous Interrupt Interface Mode
    8. 7.8  Timing Requirements: Synchronous Master Interface Mode
    9. 7.9  Switching Characteristics: Synchronous Master Interface Mode
    10. 7.10 Timing Requirements: Synchronous Slave Interface Mode
    11. 7.11 Switching Characteristics: Synchronous Slave Interface Mode
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Measurements
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Clock
        1. 9.3.1.1 XTAL1/CLKIN and XTAL2
        2. 9.3.1.2 ICLK
        3. 9.3.1.3 MODCLK
        4. 9.3.1.4 Data Rate
      2. 9.3.2 Analog Input
      3. 9.3.3 Input Overrange and Underrange Detection
      4. 9.3.4 Reference
      5. 9.3.5 ΔΣ Modulator
      6. 9.3.6 Digital Decimation Filter
      7. 9.3.7 Watchdog Timer
    4. 9.4 Device Functional Modes
      1. 9.4.1 Low-Power and High-Resolution Mode
      2. 9.4.2 Power-Up
      3. 9.4.3 Standby and Wake-Up Mode
      4. 9.4.4 Conversion Mode
      5. 9.4.5 Reset (RESET)
    5. 9.5 Programming
      1. 9.5.1 Interface Protocol
        1. 9.5.1.1 Device Word Length
        2. 9.5.1.2 Fixed versus Dynamic-Frame Mode
        3. 9.5.1.3 Command Word
        4. 9.5.1.4 Status Word
        5. 9.5.1.5 Data Words
          1. 9.5.1.5.1 ADC Data Word 16-Bit Format
          2. 9.5.1.5.2 ADC Data Word 24-Bit Format
        6. 9.5.1.6 Hamming Code Error Correction
        7. 9.5.1.7 Cyclic Redundancy Check (CRC)
          1. 9.5.1.7.1 Computing the CRC
          2. 9.5.1.7.2 CRC With CRC_MODE = 1
          3. 9.5.1.7.3 CRC with CRC_MODE = 0
          4. 9.5.1.7.4 CRC Using the WREGS Command
      2. 9.5.2 SPI Interface
        1. 9.5.2.1 Asynchronous Interrupt Mode
          1. 9.5.2.1.1 Chip Select (CS)
          2. 9.5.2.1.2 Serial Clock (SCLK)
          3. 9.5.2.1.3 Data Input (DIN)
          4. 9.5.2.1.4 Data Output (DOUT)
          5. 9.5.2.1.5 Data Ready (DRDY)
          6. 9.5.2.1.6 Asynchronous Interrupt Mode Data Retrieval
        2. 9.5.2.2 Synchronous Master Mode
          1. 9.5.2.2.1 Serial Clock (SCLK)
          2. 9.5.2.2.2 Data Input (DIN)
          3. 9.5.2.2.3 Data Output (DOUT)
          4. 9.5.2.2.4 Data Ready (DRDY)
          5. 9.5.2.2.5 Chip Select (CS)
          6. 9.5.2.2.6 Synchronous Master Mode Data Retrieval
        3. 9.5.2.3 Synchronous Slave Mode
          1. 9.5.2.3.1 Chip Select (CS)
          2. 9.5.2.3.2 Serial Clock (SCLK)
          3. 9.5.2.3.3 Data Input (DIN)
          4. 9.5.2.3.4 Data Output (DOUT)
          5. 9.5.2.3.5 Data Ready (DRDY)
          6. 9.5.2.3.6 Synchronous Slave Mode Data Retrieval
        4. 9.5.2.4 ADC Frame Complete (DONE)
      3. 9.5.3 SPI Command Definitions
        1. 9.5.3.1  NULL: Null Command
        2. 9.5.3.2  RESET: Reset to POR Values
        3. 9.5.3.3  STANDBY: Enter Standby Mode
        4. 9.5.3.4  WAKEUP: Exit Standby Mode
        5. 9.5.3.5  LOCK: Lock ADC Registers
        6. 9.5.3.6  UNLOCK: Unlock ADC Registers
          1. 9.5.3.6.1 UNLOCK from POR or RESET
        7. 9.5.3.7  RREG: Read a Single Register
        8. 9.5.3.8  RREGS: Read Multiple Registers
        9. 9.5.3.9  WREG: Write Single Register
        10. 9.5.3.10 WREGS: Write Multiple Registers
    6. 9.6 Register Maps
      1. 9.6.1 User Register Description
        1. 9.6.1.1  ID_MSB: ID Control Register MSB (address = 00h) [reset = xxh]
          1. Table 16. ID_MSB Register Field Descriptions
        2. 9.6.1.2  ID_LSB: ID Control Register LSB (address = 01h) [reset = xxh]
          1. Table 17. ID_LSB Register Field Descriptions
        3. 9.6.1.3  STAT_1: Status 1 Register (address = 02h) [reset = 00h]
          1. Table 18. STAT_1 Register Field Descriptions
        4. 9.6.1.4  STAT_P: Positive Input Fault Detect Status Register (address = 03h) [reset = 00h]
          1. Table 19. STAT_P Register Field Descriptions
        5. 9.6.1.5  STAT_N: Negative Input Fault Detect Status Register (address = 04h) [reset = 00h]
          1. Table 20. STAT_N Register Field Descriptions
        6. 9.6.1.6  STAT_S: SPI Status Register (address = 05h) [reset = 00h]
          1. Table 21. STAT_S Register Field Descriptions
        7. 9.6.1.7  ERROR_CNT: Error Count Register (address = 06h) [reset = 00h]
          1. Table 22. ERROR_CNT Register Field Descriptions
        8. 9.6.1.8  STAT_M2: Hardware Mode Pin Status Register (address = 07h) [reset = xxh]
          1. Table 23. STAT_M2 Register Field Descriptions
        9. 9.6.1.9  Reserved Registers (address = 08h to 0Ah) [reset = 00h]
          1. Table 24. Reserved Registers Field Descriptions
        10. 9.6.1.10 A_SYS_CFG: Analog System Configuration Register (address = 0Bh) [reset = 60h]
          1. Table 25. A_SYS_CFG Register Field Descriptions
        11. 9.6.1.11 D_SYS_CFG: Digital System Configuration Register (address = 0Ch) [reset = 3Ch]
          1. Table 27. D_SYS_CFG Register Field Descriptions
        12. 9.6.1.12 CLK1: Clock Configuration 1 Register (address = 0Dh) [reset = 08h]
          1. Table 28. CLK1 Register Field Descriptions
        13. 9.6.1.13 CLK2: Clock Configuration 2 Register (address = 0Eh) [reset = 86h]
          1. Table 29. CLK2 Register Field Descriptions
        14. 9.6.1.14 ADC_ENA: ADC Channel Enable Register (address = 0Fh) [reset = 00h]
          1. Table 31. ADC_ENA Register Field Descriptions
        15. 9.6.1.15 Reserved Register (address = 10h) [reset = 00h]
          1. Table 32. Reserved Register Field Descriptions
      2. 9.6.2 ADCx: ADC Channel Digital Gain Configuration Registers (address = 11h to 14h) [reset = 00h]
        1. Table 33. ADCx Registers Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Unused Inputs and Outputs
      2. 10.1.2 Power Monitoring Specific Applications
      3. 10.1.3 Multiple Device Configuration
        1. 10.1.3.1 First Device Configured in Asynchronous Interrupt Mode
        2. 10.1.3.2 First Device Configured in Synchronous Master Mode
        3. 10.1.3.3 All Devices Configured in Synchronous Slave Mode
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
    3. 10.3 What To Do and What Not To Do
    4. 10.4 Initialization Set Up
  11. 11Power Supply Recommendations
    1. 11.1 Negative Charge Pump
    2. 11.2 Internal Digital LDO
    3. 11.3 Power-Supply Sequencing
    4. 11.4 Power-Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PBS|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 Noise Measurements

Adjust the data rate and gain to optimize the ADS131A02 and ADS131A04 noise performance. When averaging is increased by reducing the data rate, noise drops correspondingly. Table 1 and Table 2 summarize the ADS131A0x noise performance with a 2.442-V reference and a 3.3-V analog power supply. Table 3 and Table 4 summarize the ADS131A02 and ADS131A04 noise performance with a 4.0-V reference and a 5-V analog power supply (or using ±2.5-V bipolar analog power supplies). The data are representative of typical noise performance at TA = 25°C when fMOD = 4.096 MHz. The data shown are typical results with the analog inputs shorted together and taking an average of multiple readings across all channels. A minimum 1 second of consecutive readings are used to calculate the RMS noise for each reading. The data are also representative of the ADS131A0x noise performance when using a low-noise external reference, such as the REF5025 or REF5040. The effective resolution data and dynamic range data in Table 1, Table 2, Table 3, and Table 4 are calculated using Equation 1 and Equation 2. The μVrms noise numbers in the tables are input-referred.

Equation 1. ADS131A02 ADS131A04 eq_effres_sbas590.gif
Equation 2. ADS131A02 ADS131A04 eq_dynamicrange_sbas590.gif

Table 1. Dynamic Range, Effective Resolution, and Noise in μVrms at 3.3-V Analog Supply, and 2.442-V Reference for Gain = 1, 2, and 4

OSR SETTING fDATA AT 4.096-MHz fMOD (kHz) GAIN
x1 x2 x4
DYNAMIC RANGE (dB) EFFECTIVE RESOLUTION (Bits) μVrms DYNAMIC RANGE (dB) EFFECTIVE RESOLUTION (Bits) μVrms DYNAMIC RANGE (dB) EFFECTIVE RESOLUTION (Bits) μVrms
4096 1.000 119.49 21.35 1.82 113.49 20.35 1.82 108.08 19.46 1.70
2048 2.000 116.47 20.85 2.58 110.97 19.94 2.44 105.22 18.98 2.36
1024 4.000 113.85 20.41 3.49 107.91 19.43 3.47 101.77 18.41 3.52
800 5.120 112.93 20.26 3.88 106.72 19.23 3.98 101.05 18.29 3.82
768 5.333 112.90 20.25 3.90 106.69 19.22 3.99 100.76 18.24 3.95
512 8.000 110.73 19.89 5.01 104.83 18.91 4.95 98.75 17.91 4.97
400 10.240 109.74 19.73 5.61 103.69 18.72 5.64 97.76 17.74 5.58
384 10.667 109.53 19.70 5.75 103.65 18.72 5.66 97.58 17.71 5.69
256 16.000 107.74 19.40 7.07 101.67 18.39 7.11 95.72 17.40 7.06
200 20.480 106.48 19.19 8.17 100.55 18.20 8.09 94.54 17.21 8.08
192 21.333 106.28 19.16 8.36 100.17 18.14 8.45 94.11 17.13 8.49
128 32.000 104.05 18.78 10.81 97.98 17.78 10.88 92.00 16.78 10.82
96 42.667 101.90 18.43 13.85 95.95 17.44 13.74 89.90 16.43 13.79
64 64.000 97.63 17.72 22.64 91.61 16.72 22.64 85.52 15.71 22.83
48 85.333 92.58 16.88 40.50 86.62 15.89 40.22 80.59 14.89 40.26
32 128.000 85.12 15.62 96.82 78.96 14.62 97.12 73.02 13.61 97.51

Table 2. Dynamic Range, Effective Resolution, and Noise in μVrms at 3.3-V Analog Supply, and 2.442-V Reference for Gain = 8 and 16

OSR SETTING fDATA AT 4.096-MHz fMOD (kHz) GAIN
x8 x16
DYNAMIC RANGE (dB) EFFECTIVE RESOLUTION (Bits) μVrms DYNAMIC RANGE (dB) EFFECTIVE RESOLUTION (Bits) μVrms
4096 1.000 101.72 18.40 1.77 95.45 17.36 1.82
2048 2.000 98.88 17.93 2.45 93.07 16.96 2.39
1024 4.000 95.97 17.44 3.43 89.82 16.42 3.48
800 5.120 95.03 17.29 3.82 88.66 16.23 3.98
768 5.333 94.63 17.22 4.00 88.41 16.19 4.09
512 8.000 92.75 16.91 4.96 87.00 15.95 4.81
400 10.240 91.84 16.76 5.51 85.62 15.72 5.64
384 10.667 91.52 16.70 5.72 85.50 15.70 5.72
256 16.000 89.57 16.38 7.16 83.58 15.38 7.14
200 20.480 88.44 16.19 8.16 82.45 15.20 8.12
192 21.333 88.26 16.16 8.32 82.12 15.14 8.44
128 32.000 86.02 15.79 10.77 79.80 14.76 11.02
96 42.667 83.91 15.44 13.74 77.72 14.41 14.00
64 64.000 79.52 14.71 22.78 73.45 13.70 22.92
48 85.333 74.60 13.89 40.14 68.47 12.87 40.66
32 128.000 66.93 12.62 97.05 60.97 11.61 97.61

Table 3. Dynamic Range, Effective Resolution, and Noise in μVrms at ±2.5-V Analog Supply, and 4.0-V Reference for Gain = 1, 2, and 4

OSR SETTING fDATA AT 4.096-MHz fMOD (kHz) GAIN
x1 x2 x4
DYNAMIC RANGE (dB) EFFECTIVE RESOLUTION (Bits) μVrms DYNAMIC RANGE (dB) EFFECTIVE RESOLUTION (Bits) μVrms DYNAMIC RANGE (dB) EFFECTIVE RESOLUTION (Bits) μVrms
4096 1.000 124.55 22.19 1.66 118.69 21.22 1.64 112.32 20.16 1.71
2048 2.000 121.47 21.68 2.38 114.98 20.60 2.51 109.58 19.70 2.34
1024 4.000 118.44 21.18 3.37 112.48 20.18 3.36 106.31 19.16 3.41
800 5.120 117.58 21.03 3.72 111.46 20.02 3.77 105.29 18.99 3.84
768 5.333 116.75 20.89 4.10 110.88 19.92 4.03 105.06 18.95 3.94
512 8.000 115.16 20.63 4.93 109.23 19.65 4.88 103.10 18.63 4.94
400 10.240 114.15 20.46 5.53 108.33 19.50 5.41 102.28 18.49 5.43
384 10.667 113.88 20.42 5.71 107.83 19.41 5.73 101.70 18.39 5.80
256 16.000 112.09 20.12 7.02 105.76 19.07 7.27 99.83 18.08 7.19
200 20.480 110.71 19.89 8.22 104.65 18.88 8.27 98.37 17.84 8.51
192 21.333 110.13 19.79 8.79 104.10 18.79 8.80 97.99 17.78 8.90
128 32.000 106.93 19.26 12.72 100.76 18.24 12.94 94.59 17.21 13.15
96 42.667 104.17 18.80 17.47 98.18 17.81 17.41 92.00 16.78 17.74
64 64.000 98.84 17.92 32.27 92.74 16.91 32.58 86.50 15.87 33.40
48 85.333 93.30 17.00 61.06 87.45 16.03 59.91 81.31 15.01 60.74
32 128.000 85.10 15.64 156.92 78.87 14.60 160.84 73.35 13.67 153.69

Table 4. Dynamic Range, Effective Resolution, and Noise in μVrms at ±2.5-V Analog Supply, and 4.0-V Reference for Gain = 8 and 16

OSR SETTING fDATA AT 4.096-MHz fMOD (kHz) GAIN
x8 x16
DYNAMIC RANGE (dB) EFFECTIVE RESOLUTION (Bits) μVrms DYNAMIC RANGE (dB) EFFECTIVE RESOLUTION (Bits) μVrms
4096 1.000 106.35 19.17 1.70 100.66 18.22 1.63
2048 2.000 103.40 18.68 2.38 97.37 17.68 2.39
1024 4.000 100.46 18.19 3.35 94.59 17.21 3.29
800 5.120 99.53 18.04 3.72 93.28 17.00 3.83
768 5.333 99.19 17.98 3.87 93.09 16.97 3.91
512 8.000 97.31 17.67 4.81 91.08 16.63 4.93
400 10.240 96.23 17.49 5.45 90.16 16.48 5.48
384 10.667 95.84 17.42 5.70 89.85 16.43 5.68
256 16.000 93.87 17.09 7.15 87.73 16.07 7.25
200 20.480 92.70 16.90 8.18 86.43 15.86 8.41
192 21.333 92.10 16.80 8.77 85.68 15.73 9.17
128 32.000 88.58 16.22 13.14 82.42 15.19 13.36
96 42.667 86.27 15.83 17.15 80.00 14.79 17.64
64 64.000 80.60 14.89 32.92 74.48 13.87 33.31
48 85.333 75.29 14.01 60.68 69.10 12.98 61.90
32 128.000 67.06 12.64 156.51 61.17 11.64 156.32