SBAS590E March   2016  – June 2020 ADS131A02 , ADS131A04

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: Asynchronous Interrupt Interface Mode
    7. 7.7  Switching Characteristics: Asynchronous Interrupt Interface Mode
    8. 7.8  Timing Requirements: Synchronous Master Interface Mode
    9. 7.9  Switching Characteristics: Synchronous Master Interface Mode
    10. 7.10 Timing Requirements: Synchronous Slave Interface Mode
    11. 7.11 Switching Characteristics: Synchronous Slave Interface Mode
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Measurements
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Clock
        1. 9.3.1.1 XTAL1/CLKIN and XTAL2
        2. 9.3.1.2 ICLK
        3. 9.3.1.3 MODCLK
        4. 9.3.1.4 Data Rate
      2. 9.3.2 Analog Input
      3. 9.3.3 Input Overrange and Underrange Detection
      4. 9.3.4 Reference
      5. 9.3.5 ΔΣ Modulator
      6. 9.3.6 Digital Decimation Filter
      7. 9.3.7 Watchdog Timer
    4. 9.4 Device Functional Modes
      1. 9.4.1 Low-Power and High-Resolution Mode
      2. 9.4.2 Power-Up
      3. 9.4.3 Standby and Wake-Up Mode
      4. 9.4.4 Conversion Mode
      5. 9.4.5 Reset (RESET)
    5. 9.5 Programming
      1. 9.5.1 Interface Protocol
        1. 9.5.1.1 Device Word Length
        2. 9.5.1.2 Fixed versus Dynamic-Frame Mode
        3. 9.5.1.3 Command Word
        4. 9.5.1.4 Status Word
        5. 9.5.1.5 Data Words
          1. 9.5.1.5.1 ADC Data Word 16-Bit Format
          2. 9.5.1.5.2 ADC Data Word 24-Bit Format
        6. 9.5.1.6 Hamming Code Error Correction
        7. 9.5.1.7 Cyclic Redundancy Check (CRC)
          1. 9.5.1.7.1 Computing the CRC
          2. 9.5.1.7.2 CRC With CRC_MODE = 1
          3. 9.5.1.7.3 CRC with CRC_MODE = 0
          4. 9.5.1.7.4 CRC Using the WREGS Command
      2. 9.5.2 SPI Interface
        1. 9.5.2.1 Asynchronous Interrupt Mode
          1. 9.5.2.1.1 Chip Select (CS)
          2. 9.5.2.1.2 Serial Clock (SCLK)
          3. 9.5.2.1.3 Data Input (DIN)
          4. 9.5.2.1.4 Data Output (DOUT)
          5. 9.5.2.1.5 Data Ready (DRDY)
          6. 9.5.2.1.6 Asynchronous Interrupt Mode Data Retrieval
        2. 9.5.2.2 Synchronous Master Mode
          1. 9.5.2.2.1 Serial Clock (SCLK)
          2. 9.5.2.2.2 Data Input (DIN)
          3. 9.5.2.2.3 Data Output (DOUT)
          4. 9.5.2.2.4 Data Ready (DRDY)
          5. 9.5.2.2.5 Chip Select (CS)
          6. 9.5.2.2.6 Synchronous Master Mode Data Retrieval
        3. 9.5.2.3 Synchronous Slave Mode
          1. 9.5.2.3.1 Chip Select (CS)
          2. 9.5.2.3.2 Serial Clock (SCLK)
          3. 9.5.2.3.3 Data Input (DIN)
          4. 9.5.2.3.4 Data Output (DOUT)
          5. 9.5.2.3.5 Data Ready (DRDY)
          6. 9.5.2.3.6 Synchronous Slave Mode Data Retrieval
        4. 9.5.2.4 ADC Frame Complete (DONE)
      3. 9.5.3 SPI Command Definitions
        1. 9.5.3.1  NULL: Null Command
        2. 9.5.3.2  RESET: Reset to POR Values
        3. 9.5.3.3  STANDBY: Enter Standby Mode
        4. 9.5.3.4  WAKEUP: Exit Standby Mode
        5. 9.5.3.5  LOCK: Lock ADC Registers
        6. 9.5.3.6  UNLOCK: Unlock ADC Registers
          1. 9.5.3.6.1 UNLOCK from POR or RESET
        7. 9.5.3.7  RREG: Read a Single Register
        8. 9.5.3.8  RREGS: Read Multiple Registers
        9. 9.5.3.9  WREG: Write Single Register
        10. 9.5.3.10 WREGS: Write Multiple Registers
    6. 9.6 Register Maps
      1. 9.6.1 User Register Description
        1. 9.6.1.1  ID_MSB: ID Control Register MSB (address = 00h) [reset = xxh]
          1. Table 16. ID_MSB Register Field Descriptions
        2. 9.6.1.2  ID_LSB: ID Control Register LSB (address = 01h) [reset = xxh]
          1. Table 17. ID_LSB Register Field Descriptions
        3. 9.6.1.3  STAT_1: Status 1 Register (address = 02h) [reset = 00h]
          1. Table 18. STAT_1 Register Field Descriptions
        4. 9.6.1.4  STAT_P: Positive Input Fault Detect Status Register (address = 03h) [reset = 00h]
          1. Table 19. STAT_P Register Field Descriptions
        5. 9.6.1.5  STAT_N: Negative Input Fault Detect Status Register (address = 04h) [reset = 00h]
          1. Table 20. STAT_N Register Field Descriptions
        6. 9.6.1.6  STAT_S: SPI Status Register (address = 05h) [reset = 00h]
          1. Table 21. STAT_S Register Field Descriptions
        7. 9.6.1.7  ERROR_CNT: Error Count Register (address = 06h) [reset = 00h]
          1. Table 22. ERROR_CNT Register Field Descriptions
        8. 9.6.1.8  STAT_M2: Hardware Mode Pin Status Register (address = 07h) [reset = xxh]
          1. Table 23. STAT_M2 Register Field Descriptions
        9. 9.6.1.9  Reserved Registers (address = 08h to 0Ah) [reset = 00h]
          1. Table 24. Reserved Registers Field Descriptions
        10. 9.6.1.10 A_SYS_CFG: Analog System Configuration Register (address = 0Bh) [reset = 60h]
          1. Table 25. A_SYS_CFG Register Field Descriptions
        11. 9.6.1.11 D_SYS_CFG: Digital System Configuration Register (address = 0Ch) [reset = 3Ch]
          1. Table 27. D_SYS_CFG Register Field Descriptions
        12. 9.6.1.12 CLK1: Clock Configuration 1 Register (address = 0Dh) [reset = 08h]
          1. Table 28. CLK1 Register Field Descriptions
        13. 9.6.1.13 CLK2: Clock Configuration 2 Register (address = 0Eh) [reset = 86h]
          1. Table 29. CLK2 Register Field Descriptions
        14. 9.6.1.14 ADC_ENA: ADC Channel Enable Register (address = 0Fh) [reset = 00h]
          1. Table 31. ADC_ENA Register Field Descriptions
        15. 9.6.1.15 Reserved Register (address = 10h) [reset = 00h]
          1. Table 32. Reserved Register Field Descriptions
      2. 9.6.2 ADCx: ADC Channel Digital Gain Configuration Registers (address = 11h to 14h) [reset = 00h]
        1. Table 33. ADCx Registers Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Unused Inputs and Outputs
      2. 10.1.2 Power Monitoring Specific Applications
      3. 10.1.3 Multiple Device Configuration
        1. 10.1.3.1 First Device Configured in Asynchronous Interrupt Mode
        2. 10.1.3.2 First Device Configured in Synchronous Master Mode
        3. 10.1.3.3 All Devices Configured in Synchronous Slave Mode
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
    3. 10.3 What To Do and What Not To Do
    4. 10.4 Initialization Set Up
  11. 11Power Supply Recommendations
    1. 11.1 Negative Charge Pump
    2. 11.2 Internal Digital LDO
    3. 11.3 Power-Supply Sequencing
    4. 11.4 Power-Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PBS|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from D Revision (January 2018) to E Revision

  • Changed Applications sectionGo
  • Changed pin diagrams to orient pin namesGo
  • Changed NC and XTAL2 pin descriptions to match Unused Connections section Go
  • Deleted common-mode input voltage from Recommended Operating Conditions tableGo
  • Added reference to Data Rate Settings table in Data Rate sectionGo
  • Changed Sinc3 Filter Settling figure and description in Digital Decimation Filter section to show ADC conversion start and data availabilityGo
  • Changed Watchdog Timer section for clarityGo
  • Changed description of Low-Power and High-Resolution Mode and Power-Up sections for clarityGo
  • Changed RESET section for clarityGo
  • Changed Device Word Length and Fixed versus Dynamic-Frame Mode sections for clarityGo
  • Added description of 16- and 24-bit data word formats to Data Words sectionGo
  • Added Communication Methods for Data Integrity Using Delta-Sigma Data Converters application report link to Hamming Code sectionGo
  • Changed Cyclic Redundancy Check sectionGo
  • Changed CRC with CRC_MODE = 1, CRC with CRC_MODE = 0, and CRC Using the WREGS Command figures to clarify CRC modesGo
  • Changed Asynchronous Interrupt Mode sectionGo
  • Changed Synchronous Master Mode sectionGo
  • Changed Synchronous Slave Mode sectionGo
  • Added address location to description of RREG and 0000 0000 to device word in Command Definitions tableGo
  • Changed STANDBY: Enter Standby Mode section for clarityGo
  • Changed ADCx registers to ADC_ENA register in WAKEUP: Exit STANDBY Mode sectionGo
  • Changed RREGS to RREG in RREG Command Status Response (Single Register Read) figure captionGo
  • Changed first command status response from 001a aaaa nnnn nnnn to 011a aaaa nnnn nnnn in RREGS: Read Multiple Registers sectionGo
  • Changed F_DRDY description in STAT_1: Status 1 Register sectionGo
  • Added All Devices Configured in Synchronous Slave Mode to include discussion of synchronization to a master clockGo
  • Changed Bipolar Analog Power Supply to Unipolar Analog Power Supply with Negative Charge Pump Enabled figures to correct power supply connectionsGo

Changes from C Revision (November 2016) to D Revision

  • Changed document title from 2- or 4-Channel, 24-Bit, Simultaneously-Sampling, Delta-Sigma ADC to 2- or 4-Channel, 24-Bit, 128-kSPS, Simultaneous-Sampling, Delta-Sigma ADCGo
  • Changed VAVDD to AVDD, VAVSS to AVSS, VGND to GND, and VIOVDD to IOVDD throughout documentGo
  • Changed Features section Go
  • Changed Description sectionGo
  • Deleted footnote 2 Go
  • Changed AVDD, AVSS, VNCP, and XTAL2 pin descriptions and footnote 1 for clarity Go
  • Changed CAP to GND Power supply voltage parameter specifications from GND – 0.3 V to 0.3 V for the minimum specification and from GND + 2.0 V to 2.0 V for the maximum specificationGo
  • Changed Analog input voltage parameter descriptions from REFEXT to AVDD to REFEXT and from REFN input to AVSS to REFNGo
  • Changed Digital input voltage parameter description to include the names of the digital input pinsGo
  • Deleted CMRR footnote from Recommended Operating Conditions tableGo
  • Added symbol to Reference input voltage parameterGo
  • Changed Offset drift parameter typical specification from 1.2 µV/°C to 2.5 µV/°C and maximum specification from 3 µV/°C to 4 µV/°CGo
  • Changed Gain drift parameter typical specification from 0.25 ppm/°C to 0.5 ppm/°C Go
  • Deleted separate AVDD PSRR specification for the ADS131A02 Go
  • Changed Reference buffer offset parameter typical specification from 170 µV to 250 µVGo
  • Changed Reference buffer offset drift parameter typical specification from 1.1 µV/°C to 4 µV/°C and maximum specification from 4.3 µV/°C to 7 µV/°CGo
  • Changed Temperature drift parameter typical specification from 4 ppm/°C to 6 ppm/°CGo
  • Deleted VNCP parameter minimum specification and changed typical specification from –1.95 V to –2 VGo
  • Changed Electrical Characteristics table so all Power-Supply subsections are condensed to one Power-Supply subsectionGo
  • Changed free-air to ambient in condition statements of Timing Requirements tablesGo
  • Changed location of several interface timing parameters to the Timing Requirements and Switching Characteristics tables from the Detailed Description section Go
  • Changed unit from ns to tCLKIN in tc(SC) and tw(SCHL) rows of Timing Requirements: Synchronous Master Interface Mode tableGo
  • Added DRDY Synchronization Timing for Synchronous Slave Mode (CLKSRC = 0) to RESET Pin and Command Timing figuresGo
  • Changed Clock section for clarification and changed setting of XTAL2 pin Go
  • Changed Clock Mode Configurations figure to include load capacitors for clarityGo
  • Changed Analog Input section for clarityGo
  • Changed Equivalent Analog Input Circuitry figureGo
  • Changed Input Overrange and Underrange Detection section for clarityGo
  • Changed location of Reference section Go
  • Changed External Reference Driver figureGo
  • Changed Internal Reference figure Go
  • Changed Digital Decimation Filter section for clarityGo
  • Deleted figure and table from Reset (RESET) sectionGo
  • Changed Fixed versus Dynamic-Frame Mode section for clarityGo
  • Changed Data Ready (DRDY) section for clarityGo
  • Changed pulldown to pullup in bulleted list of ADC Frame Complete (DONE) section Go
  • Changed description of UNLOCK from POR or RESET sectionGo
  • Changed description of RREG: Read a Single Register sectionGo
  • Changed number of registers written plus one (n+1) to number of registers written minus one in WREGS: Write Multiple Registers sectionGo
  • Changed User Register Description section for clarityGo
  • Changed Unused Inputs and Outputs section for clarityGo
  • Changed title of Multiple Device Configuration section and changed description for clarity Go
  • Changed first paragraph of First Device Configured in Asynchronous Interrupt Mode to condense data from last three paragraphs into one Go
  • Changed description of First Device Configured in Synchronous Master Mode section to condense all paragraphs into oneGo
  • Changed description of All Devices Configured in Synchronous Slave Mode section to condense all paragraphs into one Go
  • Changed ADS131A0x Configuration Sequence figureGo
  • Changed GND to AVSS in VNCP pin description of Negative Charge Pump sectionGo
  • Changed title of Internal Digital LDO sectionGo
  • Changed description of Power-Supply Sequencing sectionGo
  • Changed Bipolar Analog Power Supply to Unipolar Analog Power Supply with Negative Charge Pump Enabled figuresGo
  • Changed first sentence of Layout Example sectionGo
  • Changed ADS131A0x Layout Example figure to improve layoutGo

Changes from B Revision (September 2016) to C Revision

  • Changed document title from Analog Front-Ends for Power Monitoring, Control, and Protection to Simultaneously-Sampling, Delta-Sigma ADCGo
  • Changed ENOB to Effective Resolution in second sub-bullet of Noise Performance Features bulletGo
  • Changed effective number of bits to effective resolution in Description section Go
  • Changed format of Absolute Maximum Ratings table; specification values did not changeGo
  • Changed title of Multiple Device Effective Resolution Histogram figureGo
  • Changed Noise Measurements section Go

Changes from A Revision (March 2016) to B Revision

  • Released ADS131A02 to productionGo
  • Changed AC Performance, PSRR, THD, and SFDR parameters in Electrical Characteristics table: added rows for ADS131A02 and added ADS131A04 to rows specific to that device Go
  • Changed title of Figure 31 and Figure 32: added ADS131A04 Go
  • Added Figure 33 and Figure 34Go
  • Changed Noise Measurements section: changed Equation 1, Equation 2, Table 1, and Table 3Go
  • Added footnote to Figure 43Go
  • Changed R2 and R3 values in footnote of Figure 44Go
  • Changed Cyclic Redundancy Check (CRC) sectionGo
  • Changed description of M2 pin functionality in Hamming Code Error Correction sectionGo
  • Changed description of M0 pin functionality in SPI Interface sectionGo
  • Changed first command status response value in RREGS: Read Multiple Registers sectionGo
  • Changed Table 15: changed register bits of row 00h, default setting and register bits of row 01h, and changed bits 2-0 of 11h, 12h, 13h, and 14h rows Go
  • Changed ID_MSB: ID Control Register MSB and ID_LSB: ID Control Register LSB registersGo
  • Changed bits 2-0 of all ADCx: ADC Channel Digital Gain Configuration RegistersGo

Changes from * Revision (March 2016) to A Revision

  • Released ADS131A04 to production Go