SBASAA5
july 2023
ADS131B23-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Switching Characteristics
6.8
Timing Diagram
6.9
Typical Characteristics
7
Parameter Measurement Information
7.1
Offset Drift Measurement
7.2
Gain Drift Measurement
7.3
Noise Performance
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Naming Conventions
8.3.2
Precision Voltage References (REFA, REFB)
8.3.3
Clocking (MCLK, OSCM, OSCD)
8.3.4
ADC1y
8.3.4.1
ADC1y Input Multiplexer
8.3.4.2
ADC1y Programmable Gain Amplifier (PGA)
8.3.4.3
ADC1y ΔΣ Modulator
8.3.4.4
ADC1y Digital Filter
8.3.4.5
ADC1y Offset and Gain Calibration
8.3.4.6
ADC1y Conversion Data
8.3.5
ADC2y
8.3.5.1
ADC2y Input Multiplexer
8.3.5.2
ADC2y Programmable Gain Amplifier (PGA)
8.3.5.3
ADC2y ΔΣ Modulator
8.3.5.4
ADC2y Digital Filter
8.3.5.5
ADC2y Offset and Gain Calibration
8.3.5.6
ADC2y Sequencer
8.3.5.7
VCMy Buffers
8.3.5.8
ADC2y Measurement Configurations
8.3.5.9
ADC2y Conversion Data
8.3.6
General-Purpose Digital Inputs and Outputs (GPIO0 to GPIO4)
8.3.6.1
GPIOx PWM Output Configuration
8.3.6.2
GPIOx PWM Input Readback
8.3.7
General-Purpose Digital Inputs and Outputs (GPIO0A, GPIO1A, GPIO0B, GPIO1B)
8.3.8
Monitors and Diagnostics
8.3.8.1
Supply Monitors
8.3.8.2
Clock Monitors
8.3.8.3
Digital Monitors
8.3.8.3.1
Register Map CRC
8.3.8.3.2
Memory Map CRC
8.3.8.3.3
GPIO Readback
8.3.8.4
Communication Monitors
8.3.8.5
Fault Flags and Fault Masking
8.3.8.6
FAULT Pin
8.3.8.7
Diagnostics and Diagnostic Procedure
8.3.8.8
Indicators
8.3.8.9
Conversion and Sequence Counters
8.3.8.10
Supply Voltage Readback
8.3.8.11
Temperature Sensor (TSA)
8.3.8.12
Test DACs (TDACA, TDACB)
8.3.8.13
Open-Wire Detection
8.3.8.14
Missing Host Detection and MHD Pin
8.3.8.15
Overcurrent Comparators (OCCA, OCCB)
8.3.8.15.1
OCCA and OCCB Pins
8.3.8.15.2
Overcurrent Indication Response Time
8.4
Device Functional Modes
8.4.1
Power-Up and Reset
8.4.1.1
Power-On Reset (POR)
8.4.1.2
RESETn Pin
8.4.1.3
RESET Command
8.4.2
Operating Modes
8.4.2.1
Active Mode
8.4.2.2
Standby Mode
8.4.2.3
Power-Down Mode
8.4.3
ADC Conversion Modes
8.4.3.1
ADC1y Conversion Modes
8.4.3.1.1
Continuous-Conversion Mode
8.4.3.1.2
Single-Shot Conversion Mode
8.4.3.1.3
Global-Chop Mode
8.4.3.1.3.1
Overcurrent Indication Response Time in Global-Chop Mode
8.4.3.2
ADC2y Sequencer Operation and Sequence Modes
8.4.3.2.1
Continuous Sequence Mode
8.4.3.2.2
Single-Shot Sequence Mode
8.4.3.2.3
Synchronized Single-Shot Sequence Mode Based on ADC1y Conversion Starts
8.5
Programming
8.5.1
Serial Interface
8.5.1.1
Serial Interface Signals
8.5.1.1.1
Chip Select (CSn)
8.5.1.1.2
Serial Data Clock (SCLK)
8.5.1.1.3
Serial Data Input (SDI)
8.5.1.1.4
Serial Data Output (SDO)
8.5.1.1.5
Data Ready (DRDYn)
8.5.1.2
Serial Interface Communication Structure
8.5.1.2.1
SPI Communication Frames
8.5.1.2.2
SPI Communication Words
8.5.1.2.3
STATUS Word
8.5.1.2.4
Communication Cyclic Redundancy Check (CRC)
8.5.1.2.5
Commands
8.5.1.2.5.1
NULL (0000 0000 0000 0000b)
8.5.1.2.5.2
RESET (0000 0000 0001 0001b)
8.5.1.2.5.3
LOCK (0000 0101 0101 0101b)
8.5.1.2.5.4
UNLOCK (0000 0110 0101 0101b)
8.5.1.2.5.5
WREG (011a aaaa aaa0 0nnnb)
8.5.1.2.5.6
RREG (101a aaaa aaan nnnnb)
8.5.1.2.6
SCLK Counter
8.5.1.2.7
SPI Timeout
8.5.1.2.8
Reading ADC1A, ADC1B, and ADC2A Conversion Data
8.5.1.2.9
DRDYn Pin Behavior
8.6
Register Map
8.6.1
Registers
9
Application and Implementation
9.1
Application Information
9.1.1
Unused Inputs and Outputs
9.1.2
Minimum Interface Connections
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Current-Shunt Measurement
9.2.2.2
Battery-Pack Voltage Measurement
9.2.2.3
Shunt Temperature Measurement
9.2.3
Application Curves
9.3
Power Supply Recommendations
9.3.1
Power-Supply Options
9.3.1.1
Single Unregulated External 4-V to 16-V Supply (3.3-V Digital I/O Levels)
9.3.1.2
Single Regulated External 3.3-V Supply (3.3-V Digital IO Levels)
9.3.1.3
Single Regulated External 5-V Supply (5-V Digital I/O Levels)
9.3.2
Power-Supply Sequencing
9.3.3
Power-Supply Decoupling
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
Receiving Notification of Documentation Updates
10.3
Support Resources
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PHP|48
MPQF051B
Thermal pad, mechanical data (Package|Pins)
PHP|48
PPTD118C
Orderable Information
sbasaa5_oa
sbasaa5_pm
8.5.1.2
Serial Interface Communication Structure