The ADS131M03-Q1 allows fine adjustment of the sample phase between channels through the use of channel phase calibration. This feature is helpful when different channels are measuring the outputs of different types of sensors that have different phase responses. For example, in power metrology applications, voltage can be measured by a voltage divider, whereas current is measured using a current transformer that exhibits a phase difference between the input and output signals. The differences in phase between the voltage and current measurement must be compensated to measure the power and related parameters accurately.

The phase setting of the different channels is configured by the PHASEn[9:0] bits in the CHn_CFG register corresponding to the channel whose phase adjustment is desired. The register value is a 10-bit two's complement value corresponding to the number of modulator clock cycles of phase offset compared to a reference phase of 0 degrees.

The mechanism for achieving phase adjustment derives from the ΔΣ architecture. The ΔΣ modulator produces samples continuously at the modulator frequency, f_MOD. These samples are filtered and decimated to the output data rate by the digital filter. The ratio between f_MOD and the data rate is the oversampling ratio (OSR). Each conversion result corresponds to an OSR number of modulator samples provided to the digital filter. When the different channels of the ADS131M03-Q1 have no programmed phase offset between them, the modulator clock cycles corresponding to the conversion results of the different channels are aligned in the time domain. Figure 8-9 depicts an example scenario where the voltage input to channel 1 has no phase offset from channel 0.

However, the sample period of one channel can be shifted with respect to another. If the inputs to both channels are sinusoids of the same frequency and the samples for these channels are retrieved by the host at the same time, the effect is that the phase of the channel with the modified sample period appears shifted. Figure 8-10 depicts how the period corresponding to the samples are shifted between channels. Figure 8-11 illustrates how the samples appear as having generated a phase shift when they are retrieved by the host.

The valid setting range is from –OSR / 2 to (OSR / 2) – 1, except for OSRs greater than 1024, where the phase calibration setting is limited to –512 to 511. If a value outside of –OSR / 2 and (OSR / 2) – 1 is programmed, the device internally clips the value to the nearest limit. For example, if the OSR setting is programmed to 128 and the PHASEn[9:0] bits are programmed to 0001100100b corresponding to 100 modulator clock cycles, the device sets the phase of the channel to 63 because that value is the upper limit of phase calibration for that OSR setting. Table 8-5 gives the range of phase calibration settings for various OSR settings.

Follow these steps to create a phase shift larger than half the sample period for OSRs less than 2048:

• Create a phase shift corresponding to an integer number of sample periods by modifying the indices between channel data in software
• Use the phase calibration function of the ADS131M03-Q1 to create the remaining fractional sample period phase shift

For example, to create a phase shift of 2.25 samples between channels 0 and 1, create a phase shift of two samples by aligning sample N in the channel 0 output data stream with sample N+2 in the channel 1 output data stream in the host software. Make the remaining 0.25 sample adjustment using the ADS131M03-Q1 phase calibration function.

The phase calibration settings of the channels affect the timing of the data-ready interrupt signal, DRDY. See the Section 8.5.1.5 section for more details regarding how phase calibration affects the DRDY signal.