SBASAF2 August 2022 ADS131M06-Q1
PRODUCTION DATA
Table 8-12 lists the ADS131M06-Q1 registers. All register offset addresses not listed in Table 8-12 should be considered as reserved locations and the register contents should not be modified.
ADDRESS | REGISTER | RESET VALUE | BIT 15 | BIT 14 | BIT 13 | BIT 12 | BIT 11 | BIT 10 | BIT 9 | BIT 8 |
---|---|---|---|---|---|---|---|---|---|---|
BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 | |||
DEVICE SETTINGS AND INDICATORS (Read-Only Registers) | ||||||||||
00h | ID | 26xxh | RESERVED | CHANCNT[3:0] | ||||||
RESERVED | ||||||||||
01h | STATUS | 0500h | LOCK | F_RESYNC | REG_MAP | CRC_ERR | CRC_TYPE | RESET | WLENGTH[1:0] | |
RESERVED | RESERVED | DRDY5 | DRDY4 | DRDY3 | DRDY2 | DRDY1 | DRDY0 | |||
GLOBAL SETTINGS ACROSS CHANNELS | ||||||||||
02h | MODE | 0510h | RESERVED | REGCRC_EN | RX_CRC_EN | CRC_TYPE | RESET | WLENGTH[1:0] | ||
RESERVED | TIMEOUT | DRDY_SEL[1:0] | DRDY_HiZ | DRDY_FMT | ||||||
03h | CLOCK | 7F0Eh | RESERVED | CH5_EN | CH4_EN | CH3_EN | CH2_EN | CH1_EN | CH0_EN | |
RESERVED | OSR[2:0] | PWR[1:0] | ||||||||
04h | GAIN1 | 0000h | RESERVED | PGAGAIN3[2:0] | RESERVED | PGAGAIN2[2:0] | ||||
RESERVED | PGAGAIN1[2:0] | RESERVED | PGAGAIN0[2:0] | |||||||
05h | GAIN2 | 0000h | RESERVED | |||||||
RESERVED | PGAGAIN5[2:0] | RESERVED | PGAGAIN4[2:0] | |||||||
06h | CFG | 0600h | RESERVED | GC_DLY[3:0] | GC_EN | |||||
CD_ALLCH | CD_NUM[2:0] | CD_LEN[2:0] | CD_EN | |||||||
07h | THRSHLD_MSB | 0000h | CD_TH_MSB[15:8] | |||||||
CD_TH_MSB[7:0] | ||||||||||
08h | THRSHLD_LSB | 0000h | CD_TH_LSB[7:0] | |||||||
RESERVED | DCBLOCK[3:0] | |||||||||
CHANNEL-SPECIFIC SETTINGS | ||||||||||
09h | CH0_CHG | 0000h | PHASE0[9:2] | |||||||
PHASE0[1:0] | RESERVED | DCBLK0_DIS0 | MUX0[1:0] | |||||||
0Ah | CH0_OCAL_MSB | 0000h | OCAL0_MSB[15:8] | |||||||
OCAL0_MSB[7:0] | ||||||||||
0Bh | CH0_OCAL_LSB | 0000h | OCAL0_LSB[7:0] | |||||||
RESERVED | ||||||||||
0Ch | CH0_GCAL_MSB | 8000h | GCAL0_MSB[15:8] | |||||||
GCAL0_MSB[7:0] | ||||||||||
0Dh | CH0_GCAL_LSB | 0000h | GCAL0_LSB[7:0] | |||||||
RESERVED | ||||||||||
0Eh | CH1_CFG | 0000h | PHASE1[9:2] | |||||||
PHASE1[1:0] | RESERVED | DCBLK1_DIS0 | MUX1[1:0] | |||||||
0Fh | CH1_OCAL_MSB | 0000h | OCAL1_MSB[15:8] | |||||||
OCAL1_MSB[7:0] | ||||||||||
10h | CH1_OCAL_LSB | 0000h | OCAL1_LSB[7:0] | |||||||
RESERVED | ||||||||||
11h | CH1_GCAL_MSB | 8000h | GCAL1_MSB[15:8] | |||||||
GCAL1_MSB[7:0] | ||||||||||
12h | CH1_GCAL_LSB | 0000h | GCAL1_LSB[7:0] | |||||||
RESERVED | ||||||||||
13h | CH2_CFG | 0000h | PHASE2[9:2] | |||||||
PHASE2[1:0] | RESERVED | DCBLK2_DIS0 | MUX2[1:0] | |||||||
14h | CH2_OCAL_MSB | 0000h | OCAL2_MSB[15:8] | |||||||
OCAL2_MSB[7:0] | ||||||||||
15h | CH2_OCAL_LSB | 0000h | OCAL2_LSB[7:0] | |||||||
RESERVED | ||||||||||
16h | CH2_GCAL_MSB | 8000h | GCAL2_MSB[15:8] | |||||||
GCAL2_MSB[7:0] | ||||||||||
17h | CH2_GCAL_LSB | 0000h | GCAL2_LSB[7:0] | |||||||
RESERVED | ||||||||||
18h | CH3_CFG | 0000h | PHASE3[9:2] | |||||||
PHASE3[1:0] | RESERVED | DCBLK3_DIS0 | MUX3[1:0] | |||||||
19h | CH2_OCAL_MSB | 0000h | OCAL3_MSB[15:8] | |||||||
OCAL3_MSB[7:0] | ||||||||||
1Ah | CH2_OCAL_LSB | 0000h | OCAL3_LSB[7:0] | |||||||
RESERVED | ||||||||||
1Bh | CH2_GCAL_MSB | 8000h | GCAL3_MSB[15:8] | |||||||
GCAL3_MSB[7:0] | ||||||||||
1Ch | CH2_GCAL_LSB | 0000h | GCAL3_LSB[7:0] | |||||||
RESERVED | ||||||||||
1Dh | CH4_CFG | 0000h | PHASE4[9:2] | |||||||
PHASE4[1:0] | RESERVED | DCBLK4_DIS0 | MUX4[1:0] | |||||||
1Eh | CH4_OCAL_MSB | 0000h | OCAL4_MSB[15:8] | |||||||
OCAL4_MSB[7:0] | ||||||||||
1Fh | CH4_OCAL_LSB | 0000h | OCAL4_LSB[7:0] | |||||||
RESERVED | ||||||||||
20h | CH4_GCAL_MSB | 8000h | GCAL4_MSB[15:8] | |||||||
GCAL4_MSB[7:0] | ||||||||||
21h | CH4_GCAL_LSB | 0000h | GCAL4_LSB[7:0] | |||||||
RESERVED | ||||||||||
22h | CH5_CFG | 0000h | PHASE5[9:2] | |||||||
PHASE5[1:0] | RESERVED | DCBLK5_DIS0 | MUX5[1:0] | |||||||
23h | CH5_OCAL_MSB | 0000h | OCAL5_MSB[15:8] | |||||||
OCAL5_MSB[7:0] | ||||||||||
24h | CH5_OCAL_LSB | 0000h | OCAL5_LSB[7:0] | |||||||
RESERVED | ||||||||||
25h | CH5_GCAL_MSB | 8000h | GCAL5_MSB[15:8] | |||||||
GCAL5_MSB[7:0] | ||||||||||
26h | CH5_GCAL_LSB | 0000h | GCAL5_LSB[7:0] | |||||||
RESERVED | ||||||||||
3Eh | REGMAP_CRC | 0000h | REG_CRC[15:8] | |||||||
REG_CRC[7:0] | ||||||||||
3Fh | RESERVED | 0000h | RESERVED | |||||||
RESERVED |
Complex bit access types are encoded to fit into small table cells. Table 8-13 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
The ID register is shown in Figure 8-26 and described in Table 8-14.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CHANCNT[3:0] | ||||||
R-0010b | R-0110b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-xxxxxxxxb | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R | 0010b |
Reserved |
11:8 | CHANCNT[3:0] | R | 0110b |
Channel count |
7:0 | RESERVED | R | xxxxxxxxb |
Reserved |
The STATUS register is shown in Figure 8-27 and described in Table 8-15.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
LOCK | F_RESYNC | REG_MAP | CRC_ERR | CRC_TYPE | RESET | WLENGTH[1:0] | |
R-0b | R-0b | R-0b | R-0b | R-0b | R-1b | R-01b | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DRDY5 | DRDY4 | DRDY3 | DRDY2 | DRDY1 | DRDY0 | |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | LOCK | R | 0b | SPI interface lock indicator 0b = Unlocked (default) 1b = Locked |
14 | F_RESYNC | R | 0b | ADC resynchronization indicator. 0b = No resynchronization (default) 1b = Resynchronization occurred |
13 | REG_MAP | R | 0b | Register map CRC fault indicator 0b = No change in the register map CRC (default) 1b = Register map CRC changed |
12 | CRC_ERR | R | 0b | SPI input CRC error indicator 0b = No CRC error (default) 1b = Input CRC error occured |
11 | CRC_TYPE | R | 0b | CRC type 0b = 16 bit CCITT (default) 1b = 16 bit ANSI |
10 | RESET | R | 1b | Reset status 0b = Not reset 1b = Reset occured (default) |
9:8 | WLENGTH[1:0] | R | 01b | Data word length 00b = 16 bit 01b = 24 bits (default) 10b = 32 bits - zero padding 11b = 32 bits - sign extension for 24 bit ADC data |
7:6 | RESERVED | R | 00b | Reserved |
5 | DRDY5 | R | 0b | Channel 5 ADC data available indicator 0b = No new data available 1b = New data are available |
4 | DRDY4 | R | 0b | Channel 4 ADC data available indicator 0b = No new data available 1b = New data are available |
3 | DRDY3 | R | 0b | Channel 3 ADC data available indicator 0b = No new data available 1b = New data are available |
2 | DRDY2 | R | 0b | Channel 2 ADC data available indicator 0b = No new data available 1b = New data are available |
1 | DRDY1 | R | 0b | Channel 1 ADC data available indicator 0b = No new data available 1b = New data are available |
0 | DRDY0 | R | 0b | Channel 0 ADC data available indicator 0b = No new data available 1b = New data are available |
The MODE register is shown in Figure 8-28 and described in Table 8-16.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | REG_CRC_EN | RX_CRC_EN | CRC_TYPE | RESET | WLENGTH[1:0] | ||
R/W-00b | R/W-0b | R/W-0b | R/W-0b | R/W-1b | R/W-01b | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | DRDY_SEL[1:0] | DRDY_HiZ | DRDY_FMT | |||
R/W-000b | R/W-1b | R/W-00b | R/W-0b | R/W-0b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | RESERVED | R/W | 00b | Reserved |
13 | REG_CRC_EN | R/W | 0b | Register Map CRC enable 0b = Disabled (default) 1b = Enabled |
12 | RX_CRC_EN | R/W | 0b | SPI input CRC enable 0b = Disabled (default) 1b = Enabled |
11 | CRC_TYPE | R/W | 0b | SPI and register map CRC type 0b = 16-bit CCITT (default) 1b = 16-bit ANSI |
10 | RESET | R/W | 1b | Reset 0b = No reset 1b = Reset happened (default by definition) |
9:8 | WLENGTH[1:0] | R/W | 01b | Data word length selection 00b = 16 bits 01b = 24 bits (default) 10b = 32 bits: LSB zero padding 11b = 32 bits: MSB sign extension |
7:5 | RESERVED | R/W | 000b | Reserved |
4 | TIMEOUT | R/W | 1b | SPI Timeout enable 0b = Disabled 1b = Enabled (default) |
3:2 | DRDY_SEL[1:0] | R/W | 00b | DRDY pin signal source selection 00b = Most lagging enabled channel (default) 01b = Logic OR of all the enabled channels 10b = Most leading enabled channel 11b = Most leading enabled channel |
1 | DRDY_HiZ | R/W | 0b | DRDY pin state when conversion data is not available 0b = Logic high (default) 1b = High impedance |
0 | DRDY_FMT | R/W | 0b | DRDY signal format when conversion data is available 0b = Logic low (default) 1b = Low pulse with a fixed duration |
The CLOCK register is shown in Figure 8-29 and described in Table 8-17.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CH5_EN | CH4_EN | CH3_EN | CH2_EN | CH1_EN | CH0_EN | |
R/W-0b | R/W-0b | R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-1b |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
XTAL_DIS | EXTREF_EN | RESERVED | OSR[2:0] | PWR | |||
R/W-0b | R/W-0b | R/W-0b | R/W-011b | R/W-10b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | RESERVED | R | 00b | Reserved |
13 | CH5_EN | R/W | 1b | Channel 5 ADC enable 0b = Disabled 1b = Enabled (default) |
12 | CH4_EN | R/W | 1b | Channel 4 ADC enable 0b = Disabled 1b = Enabled (default) |
11 | CH3_EN | R/W | 1b | Channel 3 ADC enable 0b = Disabled 1b = Enabled (default) |
10 | CH2_EN | R/W | 1b | Channel 2 ADC enable 0b = Disabled 1b = Enabled (default) |
9 | CH1_EN | R/W | 1b | Channel 1 ADC enable 0b = Disabled 1b = Enabled (default) |
8 | CH0_EN | R/W | 1b | Channel 0 ADC enable 0b = Disabled 1b = Enabled (default) |
7 | XTAL_DIS | R/W | 0b | Crystal oscillator disable 0b = Enabled (default) 1b = Disabled |
6 | EXTREF_EN | R/W | 0b | External reference enable 0b = Disabled (default) 1b = Enabled |
5 | RESERVED | R/W | 0b | Reserved |
4:2 | OSR[2:0] | R/W | 011b | Modulator oversampling ratio selection 000b = 128 001b = 256 010b = 512 011b = 1024 (default) 100b = 2048 101b = 4096 110b = 8192 111b = 16384 |
1:0 | PWR | R/W | 10b | Power mode selection 00b = Very-low-power 01b = Low-power 10b = High-resolution (default) 11b = High-resolution |
The GAIN1 register is shown in Figure 8-30 and described in Table 8-18.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PGAGAIN3[2:0] | RESERVED | PGAGAIN2[2:0] | ||||
R/W-0b | R/W-000b | R/W-0b | R/W-000b | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PGAGAIN1[2:0] | RESERVED | PGAGAIN0[2:0] | ||||
R/W-0b | R/W-000b | R/W-0b | R/W-000b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R/W | 0b | Reserved |
14:12 | PGAGAIN3[2:0] | R/W | 000b | PGA gain selection for channel 3 000b = 1 (default) 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128 |
11 | RESERVED | R/W | 0b | Reserved |
10:8 | PGAGAIN2[2:0] | R/W | 000b | PGA gain selection for channel 2 000b = 1 (default) 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128 |
7 | RESERVED | R/W | 0b | Reserved |
6:4 | PGAGAIN1[2:0] | R/W | 000b | PGA gain selection for channel 1 000b = 1 (default) 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128 |
3 | RESERVED | R/W | 0b | Reserved |
2:0 | PGAGAIN0[2:0] | R/W | 000b | PGA gain selection for channel 0 000b = 1 (default) 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128 |
The GAIN2 register is shown in Figure 8-31 and described in Table 8-19.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PGAGAIN5[2:0] | RESERVED | PGAGAIN4[2:0] | ||||
R/W-0b | R/W-000b | R/W-0b | R/W-000b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:7 | RESERVED | R/W | 000000000b | Reserved |
6:4 | PGAGAIN5[2:0] | R/W | 000b | PGA gain selection for channel 5 000b = 1 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b =128 |
3 | RESERVED | R/W | 0b | Reserved |
2:0 | PGAGAIN4[2:0] | R/W | 000b | PGA gain selection for channel 4 000b = 1 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128 |
The CFG register is shown in Figure 8-32 and described in Table 8-20.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | GC_DLY[3:0] | GC_EN | |||||
R/W-000b | R/W-0011b | R/W-0b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CD_ALLCH | CD_NUM[2:0] | CD_LEN[2:0] | CD_EN | ||||
R/W-0b | R/W-000b | R/W-000b | R/W-0b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | RESERVED | R/W | 000b | Reserved |
12:9 | GC_DLY[3:0] | R/W | 0011b | Global-chop delay selection 0000b = 2 0001b = 4 0010b = 8 0011b = 16 (default) 0100b = 32 0101b = 64 0110b = 128 0111b = 256 1000b = 512 1001b = 1024 1010b = 2048 1011b = 4096 1100b = 8192 1101b = 16384 1110b = 32768 1111b = 65536 |
8 | GC_EN | R/W | 0b | Global-chop enable 0b = Disabled (default) 1b = Enabled |
7 | CD_ALLCH | R/W | 0b | Current-detect channels selection 0b = Any channel (default) 1b = All channels |
6:4 | CD_NUM[2:0] | R/W | 000b | Number of current-detect exceeded thresholds selection 000b = 1 (default) 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128 |
3:1 | CD_LEN[2:0] | R/W | 000b | Current-detect measurement length selection 000b = 128 (default) 001b = 256 010b = 512 011b = 768 100b = 1280 101b = 1792 110b = 2560 111b = 3584 |
0 | CD_EN | R/W | 0b | Current-detect mode enable 0b = Disabled (default) 1b = Enabled |
The THRSHLD_MSB register is shown in Figure 8-33 and described in Table 8-21.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CD_TH_MSB[23:16] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CD_TH_MSB[15:8] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | CD_TH_MSB[23:8] | R/W | 00000000 00000000b | Current-detect mode threshold register bits [23:8]. |
The THRSHLD_LSB register is shown in Figure 8-34 and described in Table 8-22.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CD_TH_LSB[7:0] | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DCBLOCK[3:0] | ||||||
R-0000b | R/W-0000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | CD_TH_LSB[7:0] | R/W | 00000000b | Current-detect mode threshold register bits [7:0] |
7:4 | RESERVED | R | 0000b | Reserved |
3:0 | DCBLOCK[3:0] | R/W | 0000b | DC Block filter setting |
The CH0_CFG register is shown in Figure 8-35 and described in Table 8-23.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PHASE0[9:2] | |||||||
R/W-0000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHASE0[1:0] | RESERVED | DCBLK0_DIS | MUX0[1:0] | ||||
R/W-0000000000b | R-000b | R/W-0b | R/W-00b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:6 | PHASE0[9:0] | R/W | 0000000000b | Channel 0 phase delay |
5:3 | RESERVED | R | 000b | Reserved |
2 | DCBLK0_DIS | R/W | 0b | Channel 0 DC Block filter disable 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel |
1:0 | MUX0[1:0] | R/W | 00b | Channel 0 input selection 00b = AIN0P and AIN0N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal |
The CH0_OCAL_MSB register is shown in Figure 8-36 and described in Table 8-24.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCAL0_MSB[15:8] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OCAL0_MSB[7:0] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | OCAL0_MSB[15:0] | R/W | 00000000 00000000b | Channel 0 offset calibration register bits [23:8]. |
The CH0_OCAL_LSB register is shown in Figure 8-37 and described in Table 8-25.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCAL0_LSB[7:0] | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | OCAL0_LSB[7:0] | R/W | 00000000b | Channel 0 offset calibration register bits [7:0]. |
7:0 | RESERVED | R | 00000000b | Reserved |
The CH0_GCAL_MSB register is shown in Figure 8-38 and described in Table 8-26.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GCAL0_MSB[15:8] | |||||||
R/W-1000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GCAL0_MSB[7:0] | |||||||
R/W-1000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | GCAL0_MSB | R/W | 1000000000000000b | Channel 0 gain calibration register bits [23:8] |
The CH0_GCAL_LSB register is shown in Figure 8-39 and described in Table 8-27.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GCAL0_LSB | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | GCAL0_LSB[7:0] | R/W | 00000000b | Channel 0 gain calibration register bits [7:0] |
7:0 | RESERVED | R | 00000000b | Reserved |
The CH1_CFG register is shown in Figure 8-40 and described in Table 8-28.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PHASE1[9:2] | |||||||
R/W-0000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHASE1[1:0] | RESERVED | DCBLK1_DIS | MUX1 | ||||
R/W-0000000000b | R-000b | R/W-0b | R/W-00b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:6 | PHASE1[9:0] | R/W | 0000000000b | Channel 1 phase delay |
5:3 | RESERVED | R | 000b | Reserved |
2 | DCBLK1_DIS | R/W | 0b | Channel 1 DC Block filter disable 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel |
1:0 | MUX1 | R/W | 00b | Channel 1 input selection 00b = AIN1P and AIN1N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal |
The CH1_OCAL_MSB register is shown in Figure 8-41 and described in Table 8-29.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCAL1_MSB[15:8] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OCAL1_MSB[7:0] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | OCAL1_MSB[15:0] | R/W | 00000000 00000000b | Channel 1 offset calibration register bits [23:8] |
The CH1_OCAL_LSB register is shown in Figure 8-42 and described in Table 8-30.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCAL1_LSB[7:0] | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | OCAL1_LSB[7:0] | R/W | 00000000b | Channel 1 offset calibration register bits [7:0] |
7:0 | RESERVED | R | 00000000b | Reserved |
The CH1_GCAL_MSB register is shown in Figure 8-43 and described in Table 8-31.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GCAL1_MSB[15:8] | |||||||
R/W-1000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GCAL1_MSB[7:0] | |||||||
R/W-1000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | GCAL1_MSB[15:0] | R/W | 1000000000000000b | Channel 1 gain calibration register bits [23:8] |
The CH1_GCAL_LSB register is shown in Figure 8-44 and described in Table 8-32.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GCAL1_LSB[7:0] | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | GCAL1_LSB[7:0] | R/W | 00000000b | Channel 1 gain calibration register bits [7:0] |
7:0 | RESERVED | R | 00000000b | Reserved |
The CH2_CFG register is shown in Figure 8-45 and described in Table 8-33.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PHASE2[9:2] | |||||||
R/W-0000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHASE2[1:0] | RESERVED | DCBLK2_DIS | MUX2 | ||||
R/W-0000000000b | R-000b | R/W-0b | R/W-00b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:6 | PHASE2[9:0] | R/W | 0000000000b | Channel 2 phase delay |
5:3 | RESERVED | R | 000b | Reserved |
2 | DCBLK2_DIS | R/W | 0b | Channel 2 DC Block filter disable 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel |
1:0 | MUX2 | R/W | 00b | Channel 2 input selection 00b = AIN2P and AIN2N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal |
The CH2_OCAL_MSB register is shown in Figure 8-46 and described in Table 8-34.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCAL2_MSB[15:8] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OCAL2_MSB[7:0] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | OCAL2_MSB[15:0] | R/W | 00000000 00000000b | Channel 2 offset calibration register bits [23:8] |
The CH2_OCAL_LSB register is shown in Figure 8-47 and described in Table 8-35.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCAL2_LSB[7:0] | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | OCAL2_LSB[7:0] | R/W | 00000000b | Channel 2 offset calibration register bits [7:0] |
7:0 | RESERVED | R | 00000000b | Reserved |
The CH2_GCAL_MSB register is shown in Figure 8-48 and described in Table 8-36.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GCAL2_MSB[15:8] | |||||||
R/W-1000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GCAL2_MSB[7:0] | |||||||
R/W-1000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | GCAL2_MSB[15:0] | R/W | 1000000000000000b | Channel 2 gain calibration register bits [23:8] |
The CH2_GCAL_LSB register is shown in Figure 8-49 and described in Table 8-37.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GCAL2_LSB[7:0] | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | GCAL2_LSB[7:0] | R/W | 00000000b | Channel 2 gain calibration register bits [7:0] |
7:0 | RESERVED | R | 00000000b | Reserved |
The CH3_CFG register is shown in Figure 8-50 and described in Table 8-38.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PHASE3[9:2] | |||||||
R/W-0000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHASE3[1:0] | RESERVED | DCBLK3_DIS | MUX3 | ||||
R/W-0000000000b | R-000b | R/W-0b | R/W-00b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:6 | PHASE3[9:0] | R/W | 0000000000b | Channel 3 phase delay |
5:3 | RESERVED | R | 000b | Reserved |
2 | DCBLK3_DIS | R/W | 0b | Channel 3 DC Block filter disable 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel |
1:0 | MUX3 | R/W | 00b | Channel 3 input selection 00b = AIN3P and AIN3N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal |
The CH3_OCAL_MSB register is shown in Figure 8-51 and described in Table 8-39.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCAL3_MSB[15:8] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OCAL3_MSB[7:0] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | OCAL3_MSB[15:0] | R/W | 00000000 00000000b | Channel 3 offset calibration register bits [23:8] |
The CH3_OCAL_LSB register is shown in Figure 8-52 and described in Table 8-40.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCAL3_LSB[7:0] | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | OCAL3_LSB[7:0] | R/W | 00000000b | Channel 3 offset calibration register bits [7:0] |
7:0 | RESERVED | R | 00000000b | Reserved |
The CH3_GCAL_MSB register is shown in Figure 8-53 and described in Table 8-41.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GCAL3_MSB[15:8] | |||||||
R/W-1000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GCAL3_MSB[7:0] | |||||||
R/W-1000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | GCAL3_MSB[15:0] | R/W | 1000000000000000b | Channel 3 gain calibration register bits [23:8] |
The CH3_GCAL_LSB register is shown in Figure 8-54 and described in Table 8-42.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GCAL3_LSB[7:0] | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | GCAL3_LSB[7:0] | R/W | 00000000b | Channel 3 gain calibration register bits [7:0] |
7:0 | RESERVED | R | 00000000b | Reserved |
The CH4_CFG register is shown in Figure 8-55 and described in Table 8-43.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PHASE4[9:2] | |||||||
R/W-0000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHASE4[1:0] | RESERVED | DCBLK4_DIS | MUX4 | ||||
R/W-0000000000b | R-000b | R/W-0b | R/W-00b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:6 | PHASE4[9:0] | R/W | 0000000000b | Channel 4 phase delay |
5:3 | RESERVED | R | 000b | Reserved |
2 | DCBLK4_DIS | R/W | 0b | Channel 4 DC Block filter disable 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel |
1:0 | MUX4 | R/W | 00b | Channel 4 input selection 00b = AIN4P and AIN4N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal |
The CH4_OCAL_MSB register is shown in Figure 8-56 and described in Table 8-44.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCAL4_MSB[15:8] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OCAL4_MSB[7:0] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | OCAL4_MSB[15:0] | R/W | 00000000 00000000b | Channel 4 offset calibration register bits [23:8] |
The CH4_OCAL_LSB register is shown in Figure 8-57 and described in Table 8-45.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCAL4_LSB[7:0] | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | OCAL4_LSB[7:0] | R/W | 00000000b | Channel 4 offset calibration register bits [7:0] |
7:0 | RESERVED | R | 00000000b | Reserved |
The CH4_GCAL_MSB register is shown in Figure 8-58 and described in Table 8-46.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GCAL4_MSB[15:8] | |||||||
R/W-1000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GCAL4_MSB[7:0] | |||||||
R/W-1000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | GCAL4_MSB[15:0] | R/W | 1000000000000000b | Channel 4 gain calibration register bits [23:8] |
The CH4_GCAL_LSB register is shown in Figure 8-59 and described in Table 8-47.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GCAL4_LSB[7:0] | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | GCAL4_LSB[7:0] | R/W | 00000000b | Channel 4 gain calibration register bits [7:0] |
7:0 | RESERVED | R | 00000000b | Reserved |
The CH5_CFG register is shown in Figure 8-60 and described in Table 8-48.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PHASE5[9:2] | |||||||
R/W-0000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHASE5[1:0] | RESERVED | DCBLK5_DIS | MUX5 | ||||
R/W-0000000000b | R-000b | R/W-0b | R/W-00b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:6 | PHASE5[9:0] | R/W | 0000000000b | Channel 5 phase delay |
5:3 | RESERVED | R | 000b | Reserved |
2 | DCBLK5_DIS | R/W | 0b | Channel 5 DC Block filter disable 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel |
1:0 | MUX5 | R/W | 00b | Channel 5 put selection 00b = AIN5P and AIN5N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal |
CH5_OCAL_MSB is shown in Figure 8-61 and described in Table 8-49.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCAL5_MSB[15:8] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OCAL5_MSB[7:0] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | OCAL5_MSB[15:0] | R/W | 00000000 00000000b | Channel 5 offset calibration register bits [23:8] |
The CH5_OCAL_LSB register is shown in Figure 8-62 and described in Table 8-50.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCAL5_LSB[7:0] | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | OCAL5_LSB[7:0] | R/W | 00000000b | Channel 5 offset calibration register bits [7:0] |
7:0 | RESERVED | R | 00000000b | Reserved |
The CH5_GCAL_MSB register is shown in Figure 8-63 and described in Table 8-51.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GCAL5_MSB[15:8] | |||||||
R/W-1000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GCAL5_MSB[7:0] | |||||||
R/W-1000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | GCAL5_MSB[15:0] | R/W | 1000000000000000b | Channel 5 gain calibration register bits [23:8] |
The CH5_GCAL_LSB register is shown in Figure 8-64 and described in Table 8-52.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GCAL5_LSB[7:0] | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | GCAL5_LSB[7:0] | R/W | 00000000b | Channel 5 gain calibration register bits [7:0] |
7:0 | RESERVED | R | 00000000b | Reserved |
The REGMAP_CRC register is shown in Figure 8-65 and described in Table 8-53.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
REG_CRC[15:8] | |||||||
R-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REG_CRC[7:0] | |||||||
R-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | REG_CRC[15:0] | R | 00000000 00000000b | Register map CRC value |
The RESERVED register is shown in Figure 8-66 and described in Table 8-54.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | RESERVED | R/W | 00000000 00000000b | Reserved |