at TA = 25°C, AVDD = 3 V, DVDD = 3 V,
fCLKIN = 8.192 MHz, data rate = 4 kSPS, gain = 1 with global-chop mode disabled, using internal reference
with 100-nF tied to REFIN pin, and internal oscillator disabled (unless
otherwise noted)
Gains of 8, 16, 32, 64, and 128 only
Figure 6-4 Input
Bias Current vs Gain
Figure 6-6 Start-Up Time Histogram
Figure 6-8 Input Offset Voltage vs Temperature
12
units, all channels
Figure 6-10 Long-Term Gain Drift
Figure 6-12 AC
CMRR vs AVDD Voltage
Figure 6-14 DC DVDD PSRR vs Temperature
Gain
= 1, inputs shorted
Figure 6-16 Single Device Noise Histogram at 4 kSPS
Figure 6-18 Dynamic Range vs Gain
across Power Modes
Figure 6-20 Dynamic Range vs Gain
across OSR
Figure 6-22 THD
vs Gain
Figure 6-24 Internal Reference Voltage Temperature Drift
Figure 6-26 AVDD
Current vs CLKIN Frequency
Figure 6-5 Input
Impedance vs Gain
30 units, channel 1
Figure 6-7 Input Offset Voltage vs Gain
Includes internal reference error
Figure 6-9 Gain Error vs
Temperature
Figure 6-11 DC
CMRR vs Temperature
Figure 6-13 DC AVDD PSRR vs Temperature
Figure 6-15 Input-Referred Noise vs Temperature
Gain
= 1, inputs shorted
Figure 6-17 Single Device Noise Histogram at 32 kSPS
