Table 1. Migrating from the ADS6149 Family

8.3.1 Digital Functions and Low-Latency Mode

The device has several useful digital functions such as test patterns, gain, and offset correction. All of these functions require extra clock cycles for operation and increase the overall latency and power of the device. Alternately, the device has a low-latency mode in which the raw ADC output is routed to the output data pins with a latency of 10 clock cycles. In this mode, the digital functions are bypassed. Figure 95 shows more details of the processing after the ADC.

The device is in low-latency mode after reset. In order to use any of the digital functions, the low-latency mode must first be disabled by setting the DIS LOW LATENCY register bit to 1. After this process, the respective register bits must be programmed as described in the following sections and in the Serial Register Map section.

Figure 95. Digital Processing Block Diagram

8.3.2 Gain for SFDR, SNR Trade-Off

The ADS412x and ADS414x include gain settings that can be used to improve SFDR performance. The gain is programmable from 0 dB to 6 dB (in 0.5-dB steps) using the GAIN register bits. For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 2.

The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades approximately between 0.5 dB and 1 dB. The SNR degradation is reduced at high input frequencies. As a result, the gain is very useful at high input frequencies because the SFDR improvement is significant with marginal degradation in SNR. Therefore, the gain can be used to trade-off between SFDR and SNR.

After a reset, the device is in low-latency mode and gain function is disabled. To use gain:

• First, disable the low-latency mode (DIS LOW LATENCY = 1).
• This setting enables the gain and puts the device in a 0-dB gain mode.
• For other gain settings, program the GAIN bits.

8.3.3 Offset Correction

The ADS412x and ADS414x have an internal offset correction algorithm that estimates and corrects dc offset up to ±10 mV. The correction can be enabled using the EN OFFSET CORR serial register bit. When enabled, the algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the correction loop is a function of the sampling clock frequency. The time constant can be controlled using the OFFSET CORR TIME CONSTANT register bits, as described in Table 3.

After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 1. When frozen, the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is disabled by a default after reset.

After a reset, the device is in low-latency mode and offset correction is disabled. To use offset correction:

• First, disable the low-latency mode (DIS LOW LATENCY = 1).
• Then set EN OFFSET CORR to 1 and program the required time constant.

Figure 96 shows the time response of the offset correction algorithm after being enabled.

Figure 96. Time Response of Offset Correction

8.3.4 Power-Down

The ADS412x and ADS414x have three power-down modes: power-down global, standby, and output buffer disable.

8.3.5 Output Data Format

Two output data formats are supported: twos complement and offset binary. Each mode can be selected using the DATA FORMAT serial interface register bit or controlling the DFS pin in parallel configuration mode. In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level.

8.4.1 Digital Output Information

The ADS412x and ADS414x provide either 14-bit data or 12-bit data, respectively, and an output clock synchronized with the data.

8.4.1.2 DDR LVDS Outputs

In this mode, the data bits and clock are output using low voltage differential signal (LVDS) levels. Two data bits are multiplexed and output on each LVDS differential pair, as shown in Figure 97 and Figure 98.

Figure 97. ADS412x LVDS Data Outputs

Figure 98. ADS414x LVDS Data Outputs

Even data bits (D0, D2, D4, and so forth) are output at the falling edge of CLKOUTP and the odd data bits (D1, D3, D5, and so forth) are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to capture all 14 data bits, as shown in Figure 99.

Figure 99. DDR LVDS Interface

8.4.1.3 LVDS Output Data and Clock Buffers

The equivalent circuit of each LVDS output buffer is shown in Figure 100. After reset, the buffer presents an output impedance of 100 Ω to match with the external 100-Ω termination.

The V_DIFF voltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100-Ω external termination. The V_DIFF voltage is programmable using the LVDS SWING register bits from ±125 mV to ±570 mV.

Additionally, a mode exists to double the strength of the LVDS buffer to support 50-Ω differential termination. This mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100-Ω termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH register bits for data and output clock buffers, respectively.

The buffer output impedance behaves in the same way as a source-side series termination. By absorbing reflections from the receiver end, the output impedance of buffer helps improve signal integrity.

Use the default buffer strength to match 100-Ω external termination (R_OUT = 100 Ω). To match with a 50-Ω external termination, set the LVDS STRENGTH bit (R_OUT = 50 Ω).

Figure 100. LVDS Buffer Equivalent Circuit

8.4.1.4 Parallel CMOS Interface

In CMOS mode, each data bit is output on a separate pin as the CMOS voltage level, for every clock cycle. The rising edge of the output clock CLKOUT can be used to latch data in the receiver. Figure 101 depicts the CMOS output interface.

Figure 101. CMOS Output Interface

Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade SNR. The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this degradation, the CMOS output buffers are designed with controlled drive strength. The default drive strength ensures a wide data stable window. TI recommends using short traces (one to two inches or 2.54 cm to 5.08 cm) terminated with less than 5-pF load capacitance, as shown in Figure 102.

Figure 102. Using the CMOS Data Outputs

Table 4. High-Performance Modes^(1)(2)(3)

8.5.1 Device Configuration

The ADS412x and ADS414x have several modes that can be configured using a serial programming interface, as described in Table 5, Table 6, and Table 7. In addition, the devices have two dedicated parallel pins for quickly configuring commonly used functions. The parallel pins are DFS (analog 4-level control pin) and OE (digital control pin). The analog control pins can be easily configured using a simple resistor divider (with 10% tolerance resistors).

When the serial interface is not used, the SDATA pin can also be used as a digital control pin to place the device in standby mode. To enable this functionality, the RESET pin must be tied high. In this mode, SEN and SCLK do not have any alternative functions. Keep SEN tied high and SCLK tied low on the board.

Figure 103. Simplified Diagram to Configure the DFS Pin

8.5.2 Serial Interface

The analog-to-digital converter (ADC) has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at every falling edge of SCLK when SEN is active (low). The serial data are loaded into the register at every 16th SCLK falling edge when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The first eight bits form the register address and the remaining eight bits are the register data. The interface can work with SCLK frequency from 20 MHz down to very low speeds (a few hertz) and also with a non-50% SCLK duty cycle.

8.5.3 Serial Register Readout

The serial register readout function allows the contents of the internal registers to be read back on the OVR_SDOUT pin. This readback may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC.

After power-up and device reset, the OVR_SDOUT pin functions as an over-range indicator pin by default. When the readout mode is enabled, OVR_SDOUT outputs the contents of the selected register serially:

1. Set the READOUT register bit to 1. This setting puts the device in serial readout mode and disables any further writes to the internal registers except the register at address 0. Note that the READOUT bit itself is also located in register 0. The device can exit readout mode by writing READOUT = 0. Only the contents of the register at address 0 cannot be read in the register readout mode.
2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content must be read.
3. The device serially outputs the contents (D7 to D0) of the selected register on the OVR_SDOUT pin.
4. The external controller can latch the contents at the falling edge of SCLK.
5. To exit the serial readout mode, the reset register bit READOUT = 0 enables writes into all registers of the device. At this point, the OVR_SDOUT pin becomes an over-range indicator pin.

8.6.1 Serial Register Map

Table 8 summarizes the functions supported by the serial interface.

8.6.2 Description of Serial Registers

For best performance, two special mode register bits must be enabled: HI PERF MODE 1 and HI PERF MODE 2.