The ADS41Bx9 are members of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. These devices use innovative design techniques to achieve high dynamic performance, and consume extremely low power. The analog input pins have buffers, with benefits of constant performance and input impedance across a wide frequency range. The devices are well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.
The ADS41Bx9 have features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.
The devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500 MBPS) makes using low-cost field-programmable gate array (FPGA)-based receivers possible. The devices have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50-Ω differential termination.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADS41Bx9 | VQFN (48) | 7.00 mm × 7.00 mm |
Changes from E Revision (July 2012) to F Revision
Changes from D Revision (December 2010) to E Revision
NOINDENT:
The PowerPAD is connected to DRGND.PIN | NO. | I/O | DESCRIPTION | |
---|---|---|---|---|
NAME | ADS41B49 | ADS41B29 | ||
AGND | 9, 12, 14, 17, 19, 25 | 9, 12, 14, 17, 19, 25 | I | Analog ground |
AVDD | 8, 18, 20, 22, 24, 26 | 8, 18, 20, 22, 24, 26 | I | 1.8-V analog power supply |
AVDD_BUF | 21 | 21 | I | 3.3-V input buffer supply |
CLKM | 11 | 11 | I | Differential clock input, negative |
CLKP | 10 | 10 | I | Differential clock input, positive |
CLKOUTP | 5 | 5 | O | Differential output clock, true |
CLKOUTM | 4 | 4 | O | Differential output clock, complement |
D0_D1_M | 33 | 37 | O | Differential output data D0 and D1 multiplexed, complement |
D0_D1_P | 34 | 38 | O | Differential output data D0 and D1 multiplexed, true |
D2_D3_M | 37 | 39 | O | Differential output data D2 and D3 multiplexed, complement |
D2_D3_P | 38 | 40 | O | Differential output data D2 and D3 multiplexed, true |
D4_D5_M | 39 | 41 | O | Differential output data D4 and D5 multiplexed, complement |
D4_D5_P | 40 | 42 | O | Differential output data D4 and D5 multiplexed, true |
D6_D7_M | 41 | 43 | O | Differential output data D6 and D7 multiplexed, complement |
D6_D7_P | 42 | 44 | O | Differential output data D6 and D7 multiplexed, true |
D8_D9_M | 43 | 45 | O | Differential output data D8 and D9 multiplexed, complement |
D8_D9_P | 44 | 46 | O | Differential output data D8 and D9 multiplexed, true |
D10_D11_M | 45 | 47 | O | Differential output data D10 and D11 multiplexed, complement |
D10_D11_P | 46 | 48 | O | Differential output data D10 and D11 multiplexed, true |
D12_D13_M | 47 | — | O | Differential output data D12 and D13 multiplexed, complement |
D12_D13_P | 48 | — | O | Differential output data D12 and D13 multiplexed, true |
DFS | 6 | 6 | I | Data format select input. This pin sets the DATA FORMAT (twos complement or offset binary) and the LVDS, CMOS output interface type. |
DRGND | 1, 36 | 1, 36 | I | Digital and output buffer ground |
DRVDD | 2, 35 | 2, 35 | I | 1.8-V digital and output buffer supply |
INM | 16 | 16 | I | Differential analog input, negative |
INP | 15 | 15 | I | Differential analog input, positive |
NC | 31, 32 | 31-34 | — | Do not connect |
OE | 7 | 7 | I | Output buffer enable input, active high; this pin has an internal 100-kΩ pull-up resistor to DRVDD. |
OVR_SDOUT | 3 | 3 | O | This pin functions as an out-of-range indicator after reset, when register bit READOUT = 0, and functions as a serial register readout pin when READOUT = 1. This pin is a 1.8-V CMOS output pin (running off of DRVDD). |
RESERVED | 23 | 23 | I | Digital control pin, reserved for future use |
RESET | 30 | 30 | I | Serial interface RESET input. When using the serial interface mode, the internal registers must initialize through hardware RESET by applying a high pulse on this pin or by using the software reset option; see the Serial Interface section. When RESET is tied high, the internal registers are reset to the default values. In this condition, SDATA can be used as a control pin. RESET has an internal 100-kΩ pull-down resistor. |
SCLK | 29 | 29 | I | This pin functions as a serial interface clock input when RESET is low. When RESET is high, SCLK has no function and must be tied to ground. This pin has an internal 180-kΩ pull-down resistor |
SDATA | 28 | 28 | I | This pin functions as a serial interface data input when RESET is low. When RESET is high, SDATA functions as a STANDBY control pin (see Table 7). This pin has an internal 180-kΩ pull-down resistor. |
SEN | 27 | 27 | I | This pin functions as a serial interface enable input when RESET is low. When RESET is high, SEN has no function and must be tied to AVDD. This pin has an internal 180-kΩ pull-up resistor to AVDD. |
VCM | 13 | 13 | O | Outputs the common-mode voltage that can be used externally to bias the analog input pins. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage range, AVDD | –0.3 | 2.1 | V | |
Supply voltage range, AVDD_BUF | –0.3 | 3.9 | V | |
Supply voltage range, DRVDD | –0.3 | 2.1 | V | |
Voltage between AGND and DRGND | –0.3 | 0.3 | V | |
Voltage between AVDD to DRVDD (when AVDD leads DRVDD) | –2.4 | 2.4 | V | |
Voltage between DRVDD to AVDD (when DRVDD leads AVDD) | –2.4 | 2.4 | V | |
Voltage between AVDD_BUF to DRVDD, AVDD | –4.2 | 4.2 | V | |
Voltage applied to input pins | INP, INM | –0.3 | Minimum (1.9, AVDD + 0.3) |
V |
CLKP, CLKM(2) | –0.3 | AVDD + 0.3 | ||
RESET, SCLK, SDATA, SEN, DFS | –0.3 | 3.6 | ||
Temperature | Operating free-air, TA | –40 | 125 | °C |
Operating junction, TJ | 150 | |||
Storage, Tstg | –65 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
SUPPLIES | ||||||
AVDD | Analog supply voltage | 1.7 | 1.8 | 1.9 | V | |
AVDD_BUF | Analog buffer supply voltage | 3 | 3.3 | 3.6 | V | |
DRVDD | Digital supply voltage | 1.7 | 1.8 | 1.9 | V | |
ANALOG INPUTS | ||||||
Differential input voltage range(2) | 1.5 | VPP | ||||
Input common-mode voltage | 1.7 ± 0.05 | V | ||||
Maximum analog input frequency with 1.5-VPP input amplitude(1) | 400 | MHz | ||||
Maximum analog input frequency with 1-VPP input amplitude(1) | 600 | MHz | ||||
CLOCK INPUT | ||||||
Low-speed mode enabled(3) | 20 | 80 | MSPS | |||
Low-speed mode disabled(3) | > 80 | 250 | MSPS | |||
Input clock amplitude differential (VCLKP – VCLKM) | ||||||
Sine wave, ac-coupled | 0.2 | 1.5 | VPP | |||
LVPECL, ac-coupled | 1.6 | VPP | ||||
LVDS, ac-coupled | 0.7 | VPP | ||||
LVCMOS, single-ended, ac-coupled | 1.8 | V | ||||
Input clock duty cycle | Low-speed mode enabled | 40% | 50% | 60% | ||
Low-speed mode disabled | 35% | 50% | 65% | |||
DIGITAL OUTPUTS | ||||||
CLOAD | Maximum external load capacitance from each output pin to DRGND | 5 | pF | |||
RLOAD | Differential load resistance between the LVDS output pairs (LVDS mode) | 100 | Ω | |||
TJ | Operating junction temperature | Recommended | 108 | °C | ||
Maximum rated(7) | 125 |
THERMAL METRIC(1) | ADS41B29, ADS41B49 | UNIT | |
---|---|---|---|
RGZ (VQFN) | |||
48 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 27.9 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 15.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 5.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.3 | °C/W |
ψJB | Junction-to-board characterization parameter | 5.4 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.7 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ANALOG INPUTS | ||||||
Differential input voltage range | 1.5 | VPP | ||||
Differential input resistance | At dc (see Figure 83) | 10 | kΩ | |||
Differential input capacitance (see Figure 84) |
3.5 | pF | ||||
Analog input bandwidth | 800 | MHz | ||||
Analog input common-mode current (per input pin) |
2 | µA | ||||
VCM | Common-mode output voltage | 1.7 | V | |||
VCM output current capability | 4 | mA | ||||
DC ACCURACY | ||||||
Offset error | –15 | 2.5 | 15 | mV | ||
Temperature coefficient of offset error | 0.003 | mV/°C | ||||
EGREF | Gain error as a result of internal reference inaccuracy alone |
–2 | 2 | %FS | ||
EGCHAN | Gain error of channel alone | 2.5 | %FS | |||
POWER SUPPLY | ||||||
IAVDD | Analog supply current | 99.5 | 115 | mA | ||
IAVDD_BUF | Analog input buffer supply current | 29 | 42 | mA | ||
IDRVDD | Output buffer supply current(2) | LVDS interface with 100-Ω external termination, low LVDS swing (200 mV) | 63 | mA | ||
LVDS interface with 100-Ω external termination, standard LVDS swing (350 mV) |
75 | 90 | ||||
IDRVDD output buffer supply current(2)(1) | CMOS interface(1), 8-pF external load capacitance, fIN = 2.5 MHz | 35 | mA | |||
Global power-down | 10 | 25 | mW | |||
Standby | 200 | mW |
PARAMETER | TEST CONDITIONS | ADS41B29 | ADS41B49(1) | UNIT | |||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | ||||
Resolution | 12 | 14 | Bits | ||||||
SNR | Signal-to-noise ratio, LVDS | fIN = 20 MHz | 68.4 | 69.7 | dBFS | ||||
fIN = 70 MHz | 68.3 | 69.5 | |||||||
fIN = 100 MHz | 68.3 | 69.5 | |||||||
fIN = 170 MHz | 65.5 | 68 | 66.5 | 69.1 | |||||
fIN = 300 MHz | 67.5 | 68.4 | |||||||
SINAD | Signal-to-noise and distortion ratio, LVDS | fIN = 20 MHz | 68.3 | 69.5 | dBFS | ||||
fIN = 70 MHz | 68.1 | 69.3 | |||||||
fIN = 100 MHz | 68.2 | 69.3 | |||||||
fIN = 170 MHz | 65 | 67.8 | 66 | 68.8 | |||||
fIN = 300 MHz | 66.5 | 67.4 | |||||||
SFDR | Spurious-free dynamic range | fIN = 20 MHz | 89 | 89 | dBc | ||||
fIN = 70 MHz | 85 | 85 | |||||||
fIN = 100 MHz | 87 | 87 | |||||||
fIN = 170 MHz | 71 | 82 | 72 | 82 | |||||
fIN = 300 MHz | 75 | 75 | |||||||
THD | Total harmonic distortion | fIN = 20 MHz | 85 | 85 | dBc | ||||
fIN = 70 MHz | 82 | 82 | |||||||
fIN = 100 MHz | 83 | 83 | |||||||
fIN = 170 MHz | 68 | 79.5 | 69 | 79.5 | |||||
fIN = 300 MHz | 72 | 72 | |||||||
HD2 | Second-order harmonic distortion | fIN = 20 MHz | 93 | 93 | dBc | ||||
fIN = 70 MHz | 85 | 85 | |||||||
fIN = 100 MHz | 87 | 87 | |||||||
fIN = 170 MHz | 71 | 87 | 72 | 87 | |||||
fIN = 300 MHz | 80 | 80 | |||||||
HD3 | Third-order harmonic distortion | fIN = 20 MHz | 93 | 93 | dBc | ||||
fIN = 70 MHz | 88 | 88 | |||||||
fIN = 100 MHz | 88 | 88 | |||||||
fIN = 170 MHz | 71 | 82 | 72 | 82 | |||||
fIN = 300 MHz | 75 | 75 | |||||||
Worst spur (other than second- and third-order harmonics) |
fIN = 20 MHz | 89 | 89 | dBc | |||||
fIN = 70 MHz | 90 | 90 | |||||||
fIN = 100 MHz | 90 | 90 | |||||||
fIN = 170 MHz | 76 | 88 | 77.5 | 88 | |||||
fIN = 300 MHz | 88 | 88 | |||||||
IMD | Two-tone intermodulation distortion | f1 = 185 MHz, f2 = 190 MHz, each tone at –7 dBFS |
–86 | –86 | dBFS | ||||
Input overload recovery | Recovery to within 1% (of final value) for 6-dB overload with sine-wave input | 1 | 1 | Clock cycles | |||||
PSRR | AC power-supply rejection ratio | For 100-mVPP signal on AVDD supply, up to 10 MHz | > 30 | > 30 | dB | ||||
ENOB | Effective number of bits | fIN = 170 MHz | 11 | 11.2 | LSBs | ||||
INL | Integrated nonlinearity | fIN = 170 MHz | ±1.5 | ±3.5 | ±2.5 | ±5 | LSBs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, OE) | |||||||
High-level input voltage | RESET, SCLK, SDATA, and SEN support 1.8-V and 3.3-V CMOS logic levels | 1.3 | V | ||||
OE only supports 1.8-V CMOS logic levels | 1.3 | V | |||||
Low-level input voltage | RESET, SCLK, SDATA, and SEN support 1.8-V and 3.3-V CMOS logic levels | 0.4 | V | ||||
OE only supports 1.8-V CMOS logic levels | 0.4 | V | |||||
High-level input current | SDATA, SCLK(1) | VHIGH = 1.8 V | 10 | µA | |||
SEN(3) | VHIGH = 1.8 V | 0 | µA | ||||
Low-level input current | SDATA, SCLK | VLOW = 0 V | 0 | µA | |||
SEN | VLOW = 0 V | –10 | µA | ||||
DIGITAL OUTPUTS (CMOS INTERFACE: D0 TO D13, OVR_SDOUT) | |||||||
High-level output voltage | DRVDD – 0.1 | DRVDD | V | ||||
Low-level output voltage | 0 | 0.1 | V | ||||
DIGITAL OUTPUTS (LVDS INTERFACE: D0_D1_P/M to D12_D13_P/M, CLKOUTP/M) | |||||||
VODH | High-level output voltage(2) | Standard swing LVDS | 270 | 350 | 430 | mV | |
Low swing LVDS | 200 | mV | |||||
VODL | Low-level output voltage(2) | Standard swing LVDS | –430 | –350 | –270 | mV | |
Low swing LVDS | –200 | mV | |||||
VOCM | Output common-mode voltage | 0.85 | 1.05 | 1.25 | V |
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
GENERAL | ||||||
tA | Aperture delay | 0.6 | 0.8 | 1.2 | ns | |
Variation of aperture delay between two devices at the same temperature and DRVDD supply | ±100 | ps | ||||
tJ | Aperture jitter | 100 | fS rms | |||
Wakeup time | Time to valid data after coming out of STANDBY mode | 5 | 25 | µs | ||
Time to valid data after coming out of PDN GLOBAL mode | 100 | 500 | ||||
ADC latency(6) | Gain enabled (default after reset) | 21 | Clock cycles | |||
Gain and offset correction enabled | 22 | |||||
DDR LVDS MODE | ||||||
tSU | Data setup time(3): data valid(4) to zero-crossing of CLKOUTP | 0.75(7) | 1.1 | ns | ||
tH | Data hold time(3): zero-crossing of CLKOUTP to data becoming invalid(4) | 0.35(8) | 0.6 | ns | ||
tPDI | Clock propagation delay: input clock rising edge cross-over to output clock rising edge cross-over, 1 MSPS ≤ sampling frequency ≤ 250 MSPS | 3 | 4.2 | 5.4 | ns | |
Variation of tPDI between two devices at the same temperature and DRVDD supply | ±0.6 | ns | ||||
LVDS bit clock duty cycle of differential clock, (CLKOUTP – CLKOUTM), 1 MSPS ≤ sampling frequency ≤ 250 MSPS |
42% | 48% | 54% | |||
tRISE, tFALL | Data rise and fall time: rise time measured from –100 mV to +100 mV, fall time measured from +100 mV to –100 mV, 1 MSPS ≤ sampling frequency ≤ 250 MSPS | 0.14 | ns | |||
tCLKRISE, tCLKFALL |
Output clock rise and fall time: rise time measured from –100 mV to +100 mV, fall time measured from +100 mV to –100 mV, 1 MSPS ≤ sampling frequency ≤ 250 MSPS | 0.14 | ns | |||
tOE | Output enable (OE) to data delay time to valid data after OE becomes active | 50 | 100 | ns | ||
PARALLEL CMOS MODE(5) | ||||||
tSTART | Input clock to data delay: input clock rising edge cross-over to start of data valid(4) | 1.6 | ns | |||
tDV | Data valid time interval of valid data(4) | 2.5 | 3.2 | ns | ||
tPDI | Clock propagation delay: input clock rising edge cross-over to, output clock rising edge cross-over, 1 MSPS ≤ sampling frequency ≤ 200 MSPS | 4 | 5.5 | 7 | ns | |
Output clock duty cycle of output clock (CLKOUT), 1 MSPS ≤ sampling frequency ≤ 200 MSPS |
47% | |||||
tRISE, tFALL | Data rise and fall time: rise time measured from 20% to 80% of DRVDD, fall time measured from 80% to 20% of DRVDD, 1 MSPS ≤ sampling frequency ≤ 250 MSPS | 0.35 | ns | |||
tCLKRISE, tCLKFALL |
Output clock rise and fall time: rise time measured from 20% to 80% of DRVDD, fall time measured from 80% to 20% of DRVDD, 1 MSPS ≤ sampling frequency ≤ 200 MSPS |
0.35 | ns | |||
tOE | Output enable (OE) to data delay time to valid data after OE becomes active | 20 | 40 | ns |
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
t1 | Power-on delay from power-up of AVDD and DRVDD to RESET pulse active | 1 | ms | ||
t2 | Reset pulse duration of active RESET signal that resets the serial registers | 10 | ns | ||
1(1) | µs | ||||
t3 | Delay from RESET disable to SEN active | 100 | ns |
SAMPLING FREQUENCY (MSPS) | SETUP TIME (ns) | HOLD TIME (ns) | ||||
---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | |
230 | 0.85 | 1.25 | 0.35 | 0.6 | ||
200 | 1.05 | 1.55 | 0.35 | 0.6 | ||
185 | 1.1 | 1.7 | 0.35 | 0.6 | ||
160 | 1.6 | 2.1 | 0.35 | 0.6 | ||
125 | 2.3 | 3 | 0.35 | 0.6 | ||
80 | 4.5 | 5.2 | 0.35 | 0.6 |
SAMPLING FREQUENCY (MSPS) | TIMING SPECIFIED WITH RESPECT TO OUTPUT CLOCK | ||||||||
---|---|---|---|---|---|---|---|---|---|
tSETUP (ns) | tHOLD (ns) | tPDI (ns) | |||||||
MIN | TYP | MAX | MIN | TYP | MAX | MIN | TYP | MAX | |
200 | 1 | 1.6 | 2 | 2.8 | 4 | 5.5 | 7 | ||
185 | 1.3 | 2 | 2.2 | 3 | 4 | 5.5 | 7 | ||
160 | 1.8 | 2.5 | 2.5 | 3.3 | 4 | 5.5 | 7 | ||
125 | 2.5 | 3.2 | 3.5 | 4.3 | 4 | 5.5 | 7 | ||
80 | 4.8 | 5.5 | 5.7 | 6.5 | 4 | 5.5 | 7 |
SAMPLING FREQUENCY (MSPS) | TIMING SPECIFIED WITH RESPECT TO INPUT CLOCK | |||||
---|---|---|---|---|---|---|
tSTART (ns) | tDV (ns) | |||||
MIN | TYP | MAX | MIN | TYP | MAX | |
250 | 1.6 | 2.5 | 3.2 | |||
230 | 1.1 | 2.9 | 3.5 | |||
200 | 0.3 | 3.5 | 4.2 | |||
185 | 0 | 3.9 | 4.5 | |||
170 | –1.3 | 4.3 | 5 |
SFDR = 90.3 dBc, SNR = 69.9 dBFS, SINAD = 69.8 dBFS, THD = 85.2 dBc |
SFDR = 70.7 dBc, SNR = 68.4 dBFS, SINAD = 66.3 dBFS, THD = 69.3 dBc |
Each tone at –36-dBFS amplitude, fIN1 = 185 MHz, fIN2 = 190 MHz, two-tone IMD = 89.7 dBFS, SFDR = 106.4 dBFS |
Input frequency = 170 MHz |
Input frequency = 170 MHz |
Input frequency = 10 MHz |
SFDR = 82.9 dBc, SNR = 69.3 dBFS, SINAD = 69 dBFS, THD = 80.3 dBc |
Each tone at –7-dBFS amplitude, fIN1 = 185 MHz, fIN2 = 190 MHz, two-tone IMD = 87.3 dBFS, SFDR = 96.0 dBFS |
Input frequency = 40 MHz |
Input frequency = 170 MHz |
Input frequency = 170 MHz |
Input frequency = 170 MHz |
SFDR = 89.6 dBc, SNR = 68.6 dBFS, SINAD = 68.5 dBFS, THD = 85.2 dBc |
SFDR = 70.8 dBc, SNR = 67.4 dBFS, SINAD = 65.7 dBFS, THD = 69.4 dBc |
Each tone at –36-dBFS amplitude, fIN1 = 185 MHz, fIN2 = 190 MHz, two-tone IMD = 89.8 dBFS, SFDR = 98.5 dBFS |
Input frequency = 40 MHz |
Input frequency = 170 MHz |
Input frequency = 10 MHz |
SFDR = 82.3 dBc, SNR = 68.1 dBFS, SINAD = 67.8 dBFS, THD = 79.9 dBc |
Each tone at –7-dBFS amplitude, fIN1 = 185 MHz, fIN2 = 190 MHz, two-tone IMD = 87.3 dBFS, SFDR = 85.9 dBFS |
Input frequency = 170 MHz |
Input frequency = 170 MHz |
Input frequency = 170 MHz |
Input frequency = 170 MHz |
Input frequency = 170 MHz, 50-mVPP signal superimposed on input common-mode voltage (1.7 V) | ||
|
fIN = 170 MHz; fCM = 10 MHz, 50 mVPP; SFDR = 77.69 dB; amplitude: (fIN) = –1 dBFS; (fCM) = –93.8 dBFS; (fIN + fCM) = –78.8 dBFS; (fIN – fCM) = –81 dBFS |
fIN = 10 MHz; fPSRR = 10 MHz, 50 mVPP; amplitude: (fIN) = –1 dBFS; (fPSRR) = –65.6 dBFS; (fIN + fPSRR) = –67.5 dBFS; (fIN – fPSRR) = –68.3 dBFS |