SBAS533E March   2011  – February 2023 ADS4222 , ADS4225 , ADS4226 , ADS4242 , ADS4245 , ADS4246

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions – LVDS Mode
    2.     Pin Functions – CMOS Mode
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS4246, ADS4245, ADS4242
    6. 7.6  Electrical Characteristics: ADS4226, ADS4225, ADS4222
    7. 7.7  Electrical Characteristics: General
    8. 7.8  Digital Characteristics
    9. 7.9  Timing Requirements: LVDS and CMOS Modes (1)
    10. 7.10 Serial Interface Timing Characteristics (1)
    11. 7.11 Reset Timing (Only When Serial Interface Is Used)
    12. 7.12 Typical Characteristics
      1. 7.12.1 ADS4246
      2. 7.12.2 ADS4245
      3. 7.12.3 ADS4242
      4. 7.12.4 ADS4226
      5. 7.12.5 ADS4225
      6. 7.12.6 ADS4222
      7. 7.12.7 General
      8. 7.12.8 Contour
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Drive Circuit Requirements
        2. 8.3.1.2 Driving Circuit
      2. 8.3.2 Clock Input
      3. 8.3.3 Digital Functions
      4. 8.3.4 Gain for SFDR/SNR Trade-off
      5. 8.3.5 Offset Correction
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down
        1. 8.4.1.1 Global Power-Down
        2. 8.4.1.2 Channel Standby
        3. 8.4.1.3 Input Clock Stop
    5. 8.5 Programming
      1. 8.5.1 47
      2. 8.5.2 Parallel Configuration Only
      3. 8.5.3 Serial Interface Configuration Only
      4. 8.5.4 Using Both Serial Interface and Parallel Controls
      5. 8.5.5 Parallel Configuration Details
      6. 8.5.6 Serial Interface Details
        1. 8.5.6.1 Register Initialization
        2. 8.5.6.2 Serial Register Readout
      7. 8.5.7 Digital Output Information
        1. 8.5.7.1 Output Interface
        2. 8.5.7.2 DDR LVDS Outputs
        3. 8.5.7.3 LVDS Buffer
        4. 8.5.7.4 Parallel CMOS Interface
        5. 8.5.7.5 CMOS Interface Power Dissipation
        6. 8.5.7.6 Multiplexed Mode of Operation
        7. 8.5.7.7 Output Data Format
    6. 8.6 Register Maps
      1. 8.6.1 64
      2. 8.6.2 Description Of Serial Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Analog Input
        2. 9.2.2.2 Clock Driver
        3. 9.2.2.3 Digital Interface
        4. 9.2.2.4 SNR and Clock Jitter
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Sharing DRVDD and AVDD Supplies
      2. 9.3.2 Using DC/DC Power Supplies
      3. 9.3.3 Power Supply Bypassing
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Grounding
        2. 9.4.1.2 Supply Decoupling
        3. 9.4.1.3 Exposed Pad
        4. 9.4.1.4 Routing Analog Inputs
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics: ADS4246, ADS4245, ADS4242

Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, 50% clock duty cycle, –1 dBFS differential analog input, LVDS interface, and 0-dB gain, unless otherwise noted. Minimum and maximum values are across the full temperature range:
TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.8 V.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Resolution14Bits
Signal-to-noise ratioSNRfIN = 20 MHzADS4246 (160 MSPS)72.8dBFS
ADS4245 (125 MSPS)73.4
ADS4242 (65 MSPS)73.6
fIN = 70 MHzADS4246 (160 MSPS)72.5dBFS
ADS4245 (125 MSPS)7072.9
ADS4242 (65 MSPS)69.572.5
fIN = 100 MHzADS4246 (160 MSPS)72.2dBFS
ADS4245 (125 MSPS)72.6
ADS4242 (65 MSPS)72.3
fIN = 170 MHzADS4246 (160 MSPS)6971.2dBFS
ADS4245 (125 MSPS)71.4
ADS4242 (65 MSPS)70.4
fIN = 300 MHzADS4246 (160 MSPS)69.4dBFS
ADS4245 (125 MSPS)69.3
ADS4242 (65 MSPS)69.4
Signal-to-noise and
distortion ratio		SINADfIN = 20 MHzADS4246 (160 MSPS)72.6dBFS
ADS4245 (125 MSPS)73.2
ADS4242 (65 MSPS)73.5
fIN = 70 MHzADS4246 (160 MSPS)72.1dBFS
ADS4245 (125 MSPS)6972.6
ADS4242 (65 MSPS)68.572.3
fIN = 100 MHzADS4246 (160 MSPS)71.7dBFS
ADS4245 (125 MSPS)72.3
ADS4242 (65 MSPS)72.1
fIN = 170 MHzADS4246 (160 MSPS)67.570.8dBFS
ADS4245 (125 MSPS)71.2
ADS4242 (65 MSPS)70.2
fIN = 300 MHzADS4246 (160 MSPS)68dBFS
ADS4245 (125 MSPS)68.5
ADS4242 (65 MSPS)68.2
Spurious-free dynamic rangeSFDRfIN = 20 MHzADS4246 (160 MSPS)86dBc
ADS4245 (125 MSPS)88
ADS4242 (65 MSPS)91
fIN = 70 MHzADS4246 (160 MSPS)84dBc
ADS4245 (125 MSPS)73.586
ADS4242 (65 MSPS)73.588
fIN = 100 MHzADS4246 (160 MSPS)82dBc
ADS4245 (125 MSPS)85
ADS4242 (65 MSPS)87
fIN = 170 MHzADS4246 (160 MSPS)7282dBc
ADS4245 (125 MSPS)88
ADS4242 (65 MSPS)85
fIN = 300 MHzADS4246 (160 MSPS)78dBc
ADS4245 (125 MSPS)78
ADS4242 (65 MSPS)74
Total harmonic distortionTHDfIN = 20 MHzADS4246 (160 MSPS)84dBc
ADS4245 (125 MSPS)86
ADS4242 (65 MSPS)88
fIN = 70 MHzADS4246 (160 MSPS)81dBc
ADS4245 (125 MSPS)7284
ADS4242 (65 MSPS)7285
fIN = 100 MHzADS4246 (160 MSPS)81dBc
ADS4245 (125 MSPS)83
ADS4242 (65 MSPS)85
fIN = 170 MHzADS4246 (160 MSPS)7080dBc
ADS4245 (125 MSPS)84
ADS4242 (65 MSPS)82
fIN = 300 MHzADS4246 (160 MSPS)76dBc
ADS4245 (125 MSPS)75
ADS4242 (65 MSPS)73
Second-harmonic distortionHD2fIN = 20 MHzADS4246 (160 MSPS)86dBc
ADS4245 (125 MSPS)88
ADS4242 (65 MSPS)91
fIN = 70 MHzADS4246 (160 MSPS)84dBc
ADS4245 (125 MSPS)73.586
ADS4242 (65 MSPS)73.588
fIN = 100 MHzADS4246 (160 MSPS)82dBc
ADS4245 (125 MSPS)85
ADS4242 (65 MSPS)87
fIN = 170 MHzADS4246 (160 MSPS)7282dBc
ADS4245 (125 MSPS)88
ADS4242 (65 MSPS)85
fIN = 300 MHzADS4246 (160 MSPS)78dBc
ADS4245 (125 MSPS)78
ADS4242 (65 MSPS)74
Third-harmonic distortionHD3fIN = 20 MHzADS4246 (160 MSPS)92dBc
ADS4245 (125 MSPS)93
ADS4242 (65 MSPS)95
fIN = 70 MHzADS4246 (160 MSPS)86dBc
ADS4245 (125 MSPS)73.589
ADS4242 (65 MSPS)73.590
fIN = 100 MHzADS4246 (160 MSPS)93dBc
ADS4245 (125 MSPS)89
ADS4242 (65 MSPS)96
fIN = 170 MHzADS4246 (160 MSPS)7294dBc
ADS4245 (125 MSPS)90
ADS4242 (65 MSPS)87
fIN = 300 MHzADS4246 (160 MSPS)80dBc
ADS4245 (125 MSPS)81
ADS4242 (65 MSPS)81
Worst spur
(other than second and third harmonics)		fIN = 20 MHzADS4246 (160 MSPS)90dBc
ADS4245 (125 MSPS)95
ADS4242 (65 MSPS)98
fIN = 70 MHzADS4246 (160 MSPS)92dBc
ADS4245 (125 MSPS)7894
ADS4242 (65 MSPS)7997
fIN = 100 MHzADS4246 (160 MSPS)89dBc
ADS4245 (125 MSPS)93
ADS4242 (65 MSPS)95
fIN = 170 MHzADS4246 (160 MSPS)7789dBc
ADS4245 (125 MSPS)91
ADS4242 (65 MSPS)93
fIN = 300 MHzADS4246 (160 MSPS)91dBc
ADS4245 (125 MSPS)89
ADS4242 (65 MSPS)92
Two-tone intermodulation distortionIMDf1 = 46 MHz, f2 = 50 MHz,
each tone at –7 dBFS		ADS4246 (160 MSPS)96dBFS
ADS4245 (125 MSPS)96
ADS4242 (65 MSPS)98
f1 = 185 MHz, f2 = 190 MHz,
each tone at –7 dBFS		ADS4246 (160 MSPS)83dBFS
ADS4245 (125 MSPS)92
ADS4242 (65 MSPS)92
Crosstalk20-MHz full-scale signal on channel under observation; 170-MHz full-scale signal on other channel95dB
Input overload recoveryRecovery to within 1%
(of full-scale) for 6-dB overload with sine-wave input		1Clock cycle
AC power-supply rejection ratioPSRRFor 100-mVPP signal on AVDD supply, up to 10 MHz> 30dB
Effective number of bitsENOBfIN = 70 MHz
(ADS4245, ADS4242)
fIN = 170 MHz (ADS4246)		11.5LSBs
Differential nonlinearityDNLfIN = 70 MHz
(ADS4245, ADS4242)
fIN = 170 MHz (ADS4246)		–0.97±0.5+1.7LSBs
Integrated nonlinearityINLfIN = 70 MHz
(ADS4245, ADS4242)
fIN = 170 MHz (ADS4246)		±2±5LSBs