• Ultralow Power with Single 1.8V Supply,
  CMOS Output:
  • 277mW total power at 125MSPS
• High Dynamic Performance:
  • 88dBc SFDR at 170MHz
  • 71.4dBFS SNR at 170MHz
• Crosstalk: > 90dB at 185MHz
• Programmable Gain up to 6dB for
  SNR/SFDR Trade-off
• DC Offset Correction
• Output Interface Options:
  • 1.8V parallel CMOS interface
  • Double data rate (DDR) LVDS with programmable swing:
    • Standard swing: 350mV
    • Low swing: 200mV
• Supports Low Input Clock Amplitude
  Down to 200mV_PP
• Supports Defense, Aerospace, and Medical Applications
  • Controlled Baseline
  • One Assembly and Test Site
  • One Fabrication Site
  • Available in Military (–55°C to 125°C) Temperature Range
  • Extended Product Life Cycle
  • Extended Product-Change Notification
  • Product Traceability

• Wireless Communications Infrastructure
• Software Defined Radio
• Power Amplifier Linearization

The ADS4245 is a low-speed variant of the ADS42xx ultralow-power family of dual-channel, 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high-dynamic performance, while consuming extremely low power with 1.8V supply. This topology makes the ADS4245 well-suited for multi-carrier, wide-bandwidth communications applications.

The ADS4245 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. These device includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR (double data rate) LVDS and parallel CMOS digital output interfaces are available in a compact VQFN-64 PowerPAD™ package.

The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4245 is specified over the military temperature range (–55°C to 125°C).

Block Diagram

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

At T_A = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5V_PP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.

SFDR = 89.7dBc	SINAD = 73dBFS	SNR = 73.1dBFS
THD = 88.4dBc

Figure 6-6 FFT For 20MHz Input Signal

SFDR = 73.4dBc	SINAD = 67.7dBFS	SNR = 69.2dBFS
THD = 72.3dBc

Figure 6-8 FFT For 300MHz Input Signal

Each Tone at −7dBFS Amplitude		fIN1 = 46MHz
Two−Tone IMD=96.9dBFS	SFDR=105.3dBFS	fIN2 = 50MHz

Figure 6-10 FFT For Two-Tone Input Signal

Figure 6-12 SNR vs Input Frequency

Figure 6-14 SFDR vs Gain And Input Frequency

Input Frequency = 40MHz

Figure 6-16 Performance vs Input Amplitude

Input Frequency = 40MHz

Figure 6-18 Performance vs Input Common-Mode Voltage

Input Frequency = 150MHz

Figure 6-20 SFDR vs Temperature And AVDD Supply

Input Frequency = 150MHz

Figure 6-22 Performance vs DRVDD Supply Voltage

Input Frequency = 150MHz

Figure 6-24 Performance vs Input Clock Amplitude

Input Frequency = 20MHz

Figure 6-26 Integrated Nonlinearity

SFDR = 86.7dBc	SINAD = 71.2dBFS	SNR = 71.4dBFS
THD = 83.8dBc

Figure 6-7 FFT For 170MHz Input Signal

Each Tone at −7dBFS Amplitude		fIN1 = 185MHz
Two−Tone IMD = 94dBFS	SFDR = 92.8dBFS	fIN2 = 190MHz

Figure 6-9 FFT For Two-Tone Input Signal

Figure 6-11 SFDR vs Input Frequency

Figure 6-13 SNR vs Input Frequency (CMOS)

Figure 6-15 SINAD vs Gain And Input Frequency

Input Frequency = 150MHz

Figure 6-17 Performance vs Input Amplitude

Input Frequency = 150MHz

Figure 6-19 Performance vs Input Common-Mode Voltage

Input Frequency = 150MHz

Figure 6-21 SNR vs Temperature And AVDD Supply

Input Frequency = 40MHz

Figure 6-23 Performance vs Input Clock Amplitude

Input Frequency = 10MHz

Figure 6-25 Performance vs Input Clock Duty Cycle

RMS Noise = 1.1LSB

Figure 6-27 Output Noise Histogram (With Inputs Shorted To VCM)

At T_A = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5V_PP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.

Input Frequency = 40MHz

50mVPP Signal Superimposed

on Input Common−Mode Voltage 0.95V

Figure 6-28 CMRR vs Test Signal Frequency

AVDD = 1.8V	Input Frequency = 2.5MHz

Figure 6-30 Analog Power vs Sampling Frequency

Figure 6-32 Digital Power In Various Modes (LVDS)

Input Frequency = 10MHz
50mVPP Signal Superimposed on AVDD Supply

Figure 6-29 PSRR vs Test Signal Frequency

fIN = 2.5 MHz

Figure 6-31 Digital Power LVDS CMOS

All graphs are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock. 1.5V_PP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.

Figure 6-33 Spurious-Free Dynamic Range (0dB Gain)

Figure 6-35 Signal-To-Noise Ratio (0dB Gain)

Figure 6-37 Signal-To-Noise Ratio (0dB Gain)

Figure 6-34 Spurious-Free Dynamic Range (6dB Gain)

Figure 6-36 Signal-To-Noise Ratio (6dB Gain)

Figure 6-38 Signal-To-Noise Ratio (6dB Gain)

The ADS4245 is a low-speed variant of the ADS42xx ultralow-power family of dual-channel, 14-bit analog- to-digital converters (ADCs). Innovative design techniques are used to achieve high-dynamic performance, while consuming extremely low power with 1.8V supply.

The ADS4245 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. This device includes a dc offset correction loop that can be used to cancel the ADC offset.

The ADS4245 is terminal-compatible with the previous generation ADS62P49 family of data converters; this architecture enables easy migration. However, there are some important differences between the two device generations, summarized in Table 7-1.

The device has several useful digital functions (such as test patterns, gain, and offset correction). These functions require extra clock cycles for operation and increase the overall latency and power of the device. These digital functions are disabled by default after reset and the raw ADC output is routed to the output data terminals with a latency of 16 clock cycles. Figure 7-1 shows more details of the processing after the ADC. In order to use any of the digital functions, the EN DIGITAL bit must be set to '1'. After this, the respective register bits must be programmed as described in the following sections and in the Serial Register Map section.

Figure 7-1 Digital Processing Block

The ADS4245 includes gain settings that can be used to get improved SFDR performance (compared to no gain). The gain is programmable from 0dB to 6dB (in 0.5dB steps). For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 7-2.

The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades approximately between 0.5dB and 1dB. The SNR degradation is reduced at high input frequencies. As a result, the gain is very useful at high input frequencies because the SFDR improvement is significant with marginal degradation in SNR. Therefore, the gain can be used as a trade-off between SFDR and SNR. Note that the default gain after reset is 0dB.

The ADS4245 has an internal offset corretion algorithm that estimates and corrects dc offset up to ±10mV. The correction can be enabled using the ENABLE OFFSET CORR serial register bit. Once enabled, the algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the correction loop is a function of the sampling clock frequency. The time constant can be controlled using the OFFSET CORR TIME CONSTANT register bits, as described in Table 7-3.

After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 0. Once frozen, the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is disabled by default after reset.

The ADS4245 has two power-down modes: global power-down and channel standby. These modes can be set using either the serial register bits or using the control terminals CTRL1 to CTRL3 (as shown in Table 7-4).

In this mode, the entire chip (including ADCs, internal reference, and output buffers) are powered down, resulting in reduced total power dissipation of approximately 20mW when the CTRL terminals are used and 3mW when the PDN GLOBAL serial register bit is used. The output buffers are in high-impedance state. The wake-up time from global power-down to data becoming valid in normal mode is typically 100µs.

In this mode, each ADC channel can be powered down. The internal references are active, resulting in a quick wake-up time of 50µs. The total power dissipation in standby is approximately 200mW at 160MSPS.

In addition to the previous modes, the converter enters a low-power mode when the input clock frequency falls below 1MSPS. The power dissipation is approximately 160mW.

The ADS4245 provides 14-bit digital data for each channel and an output clock synchronized with the data.

Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be selected using the serial interface register bit or by setting the proper voltage on the SEN terminal in parallel configuration mode.

In this mode, the data bits and clock are output using low-voltage differential signal (LVDS) levels. Two data bits are multiplexed and output on each LVDS differential pair, as shown in Figure 7-2.

Figure 7-2 LVDS Interface

Even data bits (D0, D2, D4, etc.) are output at the CLKOUTP rising edge and the odd data bits (D1, D3, D5, etc.) are output at the CLKOUTP falling edge. Both the CLKOUTP rising and falling edges must be used to capture all the data bits, as shown in Figure 7-3.

Figure 7-3 DDR LVDS Interface Timing

The equivalent circuit of each LVDS output buffer is shown in Figure 7-4. After reset, the buffer presents an output impedance of 100Ω to match with the external 100Ω termination.

NOTE: Default swing across 100Ω load is ±350mV. Use the LVDS SWING bits to change the swing.

Figure 7-4 LVDS Buffer Equivalent Circuit

The V_DIFF voltage is nominally 350mV, resulting in an output swing of ±350mV with 100Ω external termination. The V_DIFF voltage is programmable using the LVDS SWING register bits from ±125mV to ±570mV.

Additionally, a mode exists to double the strength of the LVDS buffer to support 50Ω differential termination, as shown in Figure 7-5. This mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100Ω termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH register bits for data and output clock buffers, respectively.

The buffer output impedance behaves in the same way as a source-side series termination. By absorbing reflections from the receiver end, it helps to improve signal integrity.

Figure 7-5 LVDS Buffer Differential Termination

In the CMOS mode, each data bit is output on separate terminals as CMOS voltage level, every clock cycle, as Figure 7-6 shows. The rising edge of the output clock CLKOUT can be used to latch data in the receiver. It is recommended to minimize the load capacitance of the data and clock output terminals by using short traces to the receiver. Furthermore, match the output data and clock traces to minimize the skew between them.

Figure 7-6 CMOS Outputs

With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every output terminal. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined by the average number of output bits switching, which is a function of the sampling frequency and the nature of the analog input signal. This relationship is shown by the formula:

Digital current as a result of CMOS output switching = C_L × DRVDD × (N × F_AVG),

where C_L = load capacitance, N × F_AVG = average number of output bits switching.

In this mode, the digital outputs of both channels are multiplexed and output on a single bus (DB[13:0] terminals), as shown in Figure 7-7. The channel A output terminals (DA[13:0]) are in 3-state. Because the output data rate on the DB bus is effectively doubled, this mode is recommended only for low sampling frequencies (less than 80MSPS). This mode can be enabled using the POWER-DOWN MODE register bits or using the CTRL[3:1] parallel terminals.

A. In multiplexed mode, both channels outputs come on the channel B output terminals.

B. Dn = bits D0, D1, D2, etc.

Figure 7-7 Multiplexed Mode Timing Diagram

Two output data formats are supported: twos complement and offset binary. The format can be selected using the DATA FORMAT serial interface register bit or by controlling the DFS terminal in parallel configuration mode.

In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive overdrive, the output code is FFFh for the ADS422x and 3FFFh for the ADS424x in offset binary output format; the output code is 7FFh for the ADS422x and 1FFFh for the ADS424x in twos complement output format. For a negative input overdrive, the output code is 0000h in offset binary output format and 800h for the ADS422x and 2000h for the ADS424x in twos complement output format.

The ADS4245 can be configured independently using either parallel interface control or serial interface programming.

To put the device into parallel configuration mode, keep RESET tied high (AVDD). Then, use the SEN, SCLK, CTRL1, CTRL2, and CTRL3 terminals to directly control certain modes of the ADC. The device can be easily configured by connecting the parallel terminals to the correct voltage levels (as described in Table 7-5 to Table 7-8). There is no need to apply a reset and SDATA can be connected to ground.

In this mode, SEN and SCLK function as parallel interface control terminals. Some frequently-used functions can be controlled using these terminals. Table 7-5 describes the modes controlled by the parallel terminals.

To enable this mode, the serial registers must first be reset to the default values and the RESET terminal must be kept low. SEN, SDATA, and SCLK function as serial interface terminals in this mode and can be used to access the internal registers of the ADC. The registers can be reset either by applying a pulse on the RESET terminal or by setting the RESET bit high. The Serial Register Map section describes the register programming and the register reset process in more detail.

For increased flexibility, a combination of serial interface registers and parallel terminal controls (CTRL1 to CTRL3) can also be used to configure the device. To enable this option, keep RESET low. The parallel interface control terminals CTRL1 to CTRL3 are available. After power-up, the device is automatically configured according to the voltage settings on these terminals (see Table 7-8). SEN, SDATA, and SCLK function as serial interface digital terminals and are used to access the internal registers of the ADC. The registers must first be reset to the default values either by applying a pulse on the RESET terminal or by setting the RESET bit to '1'. After reset, the RESET terminal must be kept low. The Serial Register Map section describes register programming and the register reset process in more detail.

The functions controlled by each parallel terminal are described in Table 7-6, Table 7-7, and Table 7-8. A simple way of configuring the parallel terminals is shown in Figure 7-8.

Figure 7-8 Simple Scheme To Configure The Parallel Terminals

The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data) terminals. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA are latched at every SCLK falling edge when SEN is active (low). The serial data are loaded into the register at every 16th SCLK falling edge when SEN is low. When the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The first eight bits form the register address and the remaining eight bits are the register data. The interface can work with SCLK frequencies from 20MHz down to very low speeds (of a few hertz) and also with non-50% SCLK duty cycle.

After power-up, the internal registers must be initialized to the default values. Initialization can be accomplished in one of two ways:

1. Either through hardware reset by applying a high pulse on the RESET terminal (of width greater than 10ns), as shown in Figure 7-9; or
2. By applying a software reset. When using the serial interface, set the RESET bit high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET terminal is kept low.

Figure 7-9 Serial Interface Timing

The device includes a mode where the contents of the internal registers can be read back. This readback mode may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. To use readback mode, follow this procedure:

1. Set the READOUT register bit to '1'. This setting disables any further writes to the registers.
2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content has to be read.
3. The device outputs the contents (D7 to D0) of the selected register on the SDOUT terminal (terminal 64).
4. The external controller can latch the contents at the SCLK falling edge.
5. To enable register writes, reset the READOUT register bit to '0'.

The serial register readout works with both CMOS and LVDS interfaces on terminal 64.

When READOUT is disabled, the SDOUT terminal is in high-impedance state. If serial readout is not used, the SDOUT terminal must float.

Figure 7-10 Serial Readout Timing Diagram

NOTE: A high pulse on the RESET terminal is required in the serial interface mode when initialized through a hardware reset. For parallel interface operation, RESET must be permanently tied high.

Figure 7-11 Reset Timing Diagram

Table 7-11 summarizes the functions supported by the serial interface.

The ADS4245 belongs to TI's ultralow-power family of dual-channel 14-bit analog-to-digital converters (ADCs). At every rising edge of the input clock, the analog input signal of each channel is simultaneously sampled. The sampled signal in each channel is converted by a pipeline of low-resolution stages. In each stage, the sampled/held signal is converted by a high-speed, low-resolution, flash sub-ADC. The difference between the stage input and the quantized equivalent is gained and propagates to the next stage. At every clock, each succeeding stage resolves the sampled input with greater accuracy. The digital outputs from all stages are combined in a digital correction logic block and digitally processed to create the final code after a data latency of 16 clock cycles. The digital output is available as either DDR LVDS or parallel CMOS and coded in either straight offset binary or binary twos complement format. The dynamic offset of the first stage sub-ADC limits the maximum analog input frequency to approximately 400MHz (with 2V_PP amplitude) or approximately 600MHz (with 1V_PP amplitude).

The ADS4245 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using internal 5kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave clock or ac-coupling for LVPECL and LVDS clock sources are shown in Figure 8-1, Figure 8-2 and Figure 8-3. The internal clock buffer is shown in Figure 8-4.

A. R_T = termination resister, if necessary.

Figure 8-1 Differential Sine-Wave Clock Driving Circuit

Figure 8-3 LVPECL Clock Driving Circuit

Figure 8-2 LVDS Clock Driving Circuit

NOTE: C_EQ is 1pF to 3pF and is the equivalent input capacitance of the clock buffer.

Figure 8-4 Internal Clock Buffer

A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1μF capacitor, as shown in Figure 8-5. For best performance, the clock inputs must be driven differentially, thereby reducing susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input.

Figure 8-5 Single-Ended Clock Driving Circuit

The analog input consists of a switched-capacitor based, differential sample-and-hold (S/H) architecture. This differential topology results in very good ac performance even for high input frequencies at high sampling rates. The INP and INM terminals must be externally biased around a common-mode voltage of 0.95V, available on the VCM terminal. For a full-scale differential input, each input terminal (INP and INM) must swing symmetrically between VCM + 0.5V and VCM – 0.5V, resulting in a 2V_PP differential input swing. The input sampling circuit has a high 3dB bandwidth that extends up to 550MHz (measured from the input terminals to the sampled voltage). Figure 8-6 shows an equivalent circuit for the analog input.

Figure 8-6 Analog Input Equivalent Circuit

For optimum performance, the analog inputs must be driven differentially. This operation improves the common-mode noise immunity and even-order harmonic rejection. A 5Ω to 15Ω resistor in series with each input terminal is recommended to damp out ringing caused by package parasitics.

SFDR performance can be limited as a result of several reasons, including the effects of sampling glitches; nonlinearity of the sampling circuit; and nonlinearity of the quantizer that follows the sampling circuit. Depending on the input frequency, sample rate, and input amplitude, one of these factors plays a dominant part in limiting performance. At very high input frequencies (greater than approximately 300MHz), SFDR is determined largely by the device sampling circuit nonlinearity. At low input amplitudes, the quantizer nonlinearity usually limits performance.

Glitches are caused by the opening and closing of the sampling switches. The driving circuit should present a low source impedance to absorb these glitches. Otherwise, glitches could limit performance, primarily at low input frequencies (up to approximately 200MHz). It is also necessary to present low impedance (less than 50Ω) for the common-mode switching currents. This configuration can be achieved by using two resistors from each input terminated to the common-mode voltage (VCM).

The device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the sampling glitches inside the device itself. The cutoff frequency of the R-C filter involves a trade-off. A lower cutoff frequency (larger C) absorbs glitches better, but it reduces the input bandwidth. On the other hand, with a higher cutoff frequency (smaller C), bandwidth support is maximized. However, the sampling glitches now must be supplied by the external drive circuit. This tradeoff has limitations as a result of the presence of the package bond-wire inductance.

In the ADS4245, the R-C component values have been optimized while supporting high input bandwidth (up to 550MHz). However, in applications with input frequencies up to 200MHz to 300MHz, the filtering of the glitches can be improved further using an external R-C-R filter; see Figure 8-7 and Figure 8-8.

Two example driving circuit configurations are shown in Figure 8-7 and Figure 8-8—one optimized for low bandwidth (low input frequencies) and the other one for high bandwidth to support higher input frequencies. Note that both of the drive circuits have been terminated by 50Ω near the ADC side. The termination is accomplished by a 25Ω resistor from each input to the 1.5V common-mode (VCM) from the device. This architecture allows the analog inputs to be biased around the required common-mode voltage.

The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch; good performance is obtained for high-frequency input signals. An additional termination resistor pair may be required between the two transformers, as shown in Figure 8-7, Figure 8-8, and Figure 8-9. The center point of this termination is connected to ground to improve the balance between the P and M sides. The values of the terminations between the transformers and on the secondary side must be chosen to obtain an effective 50Ω (in the case of 50Ω source impedance).

Figure 8-7 Drive Circuit With Low Bandwidth (For Low Input Frequencies Less Than 150MHz)

Figure 8-8 Drive Circuit With High Bandwidth (For High Input Frequencies Greater Than 150MHz And Less Than 270MHz)

Figure 8-9 Drive Circuit With Very High Bandwidth (Greater Than 270MHz)

All of these examples show 1:1 transformers being used with a 50Ω source. As explained in the Drive Circuit Requirements section, this configuration helps to present a low source impedance to absorb the sampling glitches. With a 1:4 transformer, the source impedance is 200Ω. The higher source impedance is unable to absorb the sampling glitches effectively and can lead to degradation in performance (compared to using 1:1 transformers).

In almost all cases, either a band-pass or low-pass filter is required to obtain the desired dynamic performance, as shown in Figure 8-10. Such filters present low source impedance at the high frequencies corresponding to the sampling glitch and help avoid the performance loss with the high source impedance.

Figure 8-10 Drive Circuit With A 1:4 Transformer

In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. Furthermore, the ADC input impedance must be considered. Figure 8-11 and Figure 8-12 show the impedance (Z_IN = R_IN || C_IN) looking into the ADC input terminals.

Figure 8-11 ADC Analog Input Resistance (R_IN) Across Frequency

Figure 8-12 ADC Analog Input Capacitance (C_IN) Across Frequency

The recommended analog/digital power supply range for ADS4245 is 1.7V to 1.9V.

A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of the board are cleanly partitioned. See the ADS4226 Evaluation Module (SLAU333) for details on layout and grounding.

Because the ADS4245 already includes internal decoupling, minimal external decoupling can be used without loss in performance. Note that decoupling capacitors can help filter external power-supply noise; thus, the optimum number of capacitors depends on the actual application. The decoupling capacitors should be placed very close to the converter supply terminals.

In addition to providing a path for heat dissipation, the PowerPAD is also electrically connected internally to the digital ground. Therefore, it is necessary to solder the exposed pad to the ground plane for best thermal and electrical performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and QFN/SON PCB Attachment (SLUA271).

It is advisable to route differential analog input pairs (INP_x and INM_x) close to each other. To minimize the possibility of coupling from a channel analog input to the sampling clock, the analog input pairs of both channels should be routed perpendicular to the sampling clock. See the ADS4226 Evaluation Module (SLAU333) for reference routing.

Figure 10-1 shows a snapshot of the PCB layout from the ADS424x EVM.

Figure 10-1 ADS42XX EVM PCB Layout

Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low-frequency value.

Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. This delay is different across channels. The maximum variation is specified as aperture delay variation (channel-to-channel).

Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.

Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle.

Maximum Conversion Rate – The maximum sampling rate at which specified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted.

Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.

Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly 1LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.

Integral Nonlinearity (INL) – The INL is the deviation of the ADC transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs.

Gain Error – Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a result of reference inaccuracy (E_GREF) and error as a result of the channel (E_GCHAN). Both errors are specified independently as E_GREF and E_GCHAN.

To a first-order approximation, the total gain error is E_TOTAL ~ E_GREF + E_GCHAN.

For example, if E_TOTAL = ±0.5%, the full-scale input varies from (1 – 0.5/100) x FS_ideal to (1 + 0.5/100) x FS_ideal.

Offset Error – The offset error is the difference, given in number of LSBs, between the ADC actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.

Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from T_MIN to T_MAX. It is calculated by dividing the maximum deviation of the parameter across the T_MIN to T_MAX range by the difference T_MAX – T_MIN.

Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (P_S) to the noise floor power (P_N), excluding the power at dc and the first nine harmonics.

Equation 1.

SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.

Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (P_S) to the power of all the other spectral components including noise (P_N) and distortion (P_D), but excluding dc.

Equation 2.

SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.

Effective Number of Bits (ENOB) – ENOB is a measure of the converter performance as compared to the theoretical limit based on quantization noise.

Equation 3.

Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (P_S) to the power of the first nine harmonics (P_D).

Equation 4.

THD is typically given in units of dBc (dB to carrier).

Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).

Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f₁ and f₂) to the power of the worst spectral component at either frequency 2f₁ – f₂ or 2f₂ – f₁. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.

DC Power-Supply Rejection Ratio (DC PSRR) – DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The dc PSRR is typically given in units of mV/V.

AC Power-Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the supply voltage by the ADC. If ΔV_SUP is the change in supply voltage and ΔV_OUT is the resultant change of the ADC output code (referred to the input), then:

Equation 5.

Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an overload on the analog inputs. This is tested by separately applying a sine wave signal with 6 dB positive and negative overload. The deviation of the first few samples after the overload (from the expected values) is noted.

Common-Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input common-mode by the ADC. If ΔV_{CM_IN} is the change in the common-mode voltage of the input terminals and ΔV_OUT is the resulting change of the ADC output code (referred to the input), then:

Equation 6.

Crosstalk (only for multi-channel ADCs) – This is a measure of the internal coupling of a signal from an adjacent channel into the channel of interest. It is specified separately for coupling from the immediate neighboring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel input. It is typically expressed in dBc.

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