SBAS653B April   2014  – October 2020 ADS4245-EP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics:
    6. 6.6  Electrical Characteristics: General
    7. 6.7  Digital Characteristics
    8. 6.8  Timing Characteristics: LVDS And CMOS Modes
    9. 6.9  Typical Characteristics:
    10. 6.10 Typical Characteristics: General
    11. 6.11 Typical Characteristics: Contour
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Functions
      2. 7.4.2 Gain For SFDR/SNR Trade-Off
      3. 7.4.3 Offset Correction
      4. 7.4.4 Power-Down
        1. 7.4.4.1 Global Power-Down
        2. 7.4.4.2 Channel Standby
        3. 7.4.4.3 Input Clock Stop
      5. 7.4.5 Digital Output Information
        1. 7.4.5.1 Output Interface
        2. 7.4.5.2 DDR LVDS Outputs
        3. 7.4.5.3 LVDS Buffer
        4. 7.4.5.4 Parallel CMOS Interface
        5. 7.4.5.5 CMOS Interface Power Dissipation
        6. 7.4.5.6 Multiplexed Mode Of Operation
        7. 7.4.5.7 Output Data Format
      6. 7.4.6 Device Configuration
        1. 7.4.6.1 Parallel Configuration Only
        2. 7.4.6.2 Serial Interface Configuration Only
        3. 7.4.6.3 Using Both Serial Interface And Parallel Controls
        4. 7.4.6.4 Parallel Configuration Details
        5. 7.4.6.5 Serial Interface Details
          1. 7.4.6.5.1 Register Initialization
          2. 7.4.6.5.2 Serial Register Readout
    5. 7.5 Serial Register Map
    6. 7.6 Description Of Serial Registers
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Clock Input
    2. 8.2 Typical Applications
      1. 8.2.1 Analog Input
        1. 8.2.1.1 Design Requirements for Drive Circuits
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Grounding
      2. 10.1.2 Supply Decoupling
      3. 10.1.3 Exposed Pad
      4. 10.1.4 Routing Analog Inputs
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Support
        1. 11.1.1.1 Definition Of Specifications
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics: General

Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, and –1dBFS differential analog input (unless otherwise noted). Minimum and maximum values are across the recommended operating condition (unless otherwise noted), AVDD = 1.8V, and DRVDD = 1.8V.
PARAMETERMINTYPMAXUNIT
ANALOG INPUTS
Differential input voltage range (0dB gain)2VPP
Differential input resistance (at 200MHz)0.75kΩ
Differential input capacitance (at 200MHz)3.7pF
Analog input bandwidth
(with 50Ω source impedance, and 50Ω termination)		550MHz
Analog input common-mode current
(per input terminal of each channel)		1.5µA/MSPS
Common-mode output voltageVCM0.95V
VCM output current capability4mA
DC ACCURACY
Offset error–252.525mV
Temperature coefficient of offset error0.003mV/°C
Gain error as a result of internal reference inaccuracy aloneEGREF–44%FS
Gain error of channel aloneEGCHAN±0.1%FS
Temperature coefficient of EGCHAN0.002Δ%/°C
POWER SUPPLY
IAVDD
Analog supply current		105130mA
IDRVDD
Output buffer supply current
LVDS interface, 350mV swing with 100Ω external termination, fIN = 2.5MHz		99120mA
IDRVDD
Output buffer supply current
CMOS interface, no load capacitance(1)
fIN = 2.5MHz		49mA
Analog power189mW
Digital power
LVDS interface, 350mV swing with 100Ω external termination, fIN = 2.5MHz		179mW
Digital power
CMOS interface, no load capacitance(1)
fIN = 2.5MHz		88mW
Global power-down25mW
(1) In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output terminals, input frequency, and the supply voltage (see the CMOS Interface Power Dissipation section in the Application Information).