The ADS424x and ADS422x family of devices are low-speed variants of the ADS42xx ultralow-power family of dual-channel, 14-bit or 12-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high-dynamic performance, while consuming extremely low power with 1.8-V supply. This topology makes the ADS424x/422x well-suited for multi-carrier, wide-bandwidth communications applications.
PART NUMBER | PACKAGE(1) | BODY SIZE (NOM) |
---|---|---|
ADS4222 | VQFN (64) | 9.00 mm × 9.00 mm |
ADS4225 | ||
ADS4226 | ||
ADS4242 | ||
ADS4245 | ||
ADS4246 |
Changes from Revision D (December 2015) to Revision E (February 2023)
Changes from Revision C (March 2011) to Revision D (December 2015)
Changes from Revision B (May 2011) to Revision C (March 2011)
Changes from Revision A (May 2011) to Revision B (May 2011)
The ADS424x/422x have gain options that can be used to improve SFDR performance at lower full-scale input ranges. These devices include a dc offset correction loop that can be used to cancel the ADC offset. Both DDR (double data rate) LVDS and parallel CMOS digital output interfaces are available in a compact VQFN-64 package.
The devices include internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. All devices are specified over the industrial temperature range (–40°C to 85°C).
DEVICE FAMILY(1) | 250 MSPS | 160 MSPS | 125 MSPS | 65 MSPS |
---|---|---|---|---|
ADS424x 14-bit family |
ADS4249 | ADS4246 | ADS4245 | ADS4242 |
ADS422x 12-bit family |
ADS4229 | ADS4226 | ADS4225 | ADS4222 |
PIN | TYPE | DESCRIPTION | ||
---|---|---|---|---|
NAME | ADS4246, 45,42 | ADS4226, 25, 22 | ||
AGND | 17, 18, 21, 24, 27, 28, 31, 32 | 17, 18, 21, 24, 27, 28, 31, 32 | Input | Analog ground |
AVDD | 16, 22, 33, 34 | 16, 22, 33, 34 | Input | Analog power supply |
CLKM | 26 | 26 | Input | Differential clock negative input |
CLKOUTM | 56 | 56 | Output | Differential output clock, complement |
CLKOUTP | 57 | 57 | Output | Differential output clock, true |
CLKP | 25 | 25 | Input | Differential clock positive input |
CTRL1 | 35 | 35 | Input | Digital control input pins. Together, they control the various power-down modes. |
CTRL2 | 36 | 36 | Input | Digital control input pins. Together, they control the various power-down modes. |
CTRL3 | 37 | 37 | Input | Digital control input pins. Together, they control the various power-down modes. |
DA0P | 41 | 43 | Output | Channel A differential output data pair, D0 and D1 multiplexed |
DA0M | 40 | 42 | Output | Channel A differential output data pair, D0 and D1 multiplexed |
DA2P | 43 | 45 | Output | Channel A differential output data D2 and D3 multiplexed |
DA2M | 42 | 44 | Output | Channel A differential output data D2 and D3 multiplexed |
DA4P | 45 | 47 | Output | Channel A differential output data D4 and D5 multiplexed |
DA4M | 44 | 46 | Output | Channel A differential output data D4 and D5 multiplexed |
DA6P | 47 | 51 | Output | Channel A differential output data D6 and D7 multiplexed |
DA6M | 46 | 50 | Output | Channel A differential output data D6 and D7 multiplexed |
DA8P | 51 | 53 | Output | Channel A differential output data D8 and D9 multiplexed |
DA8M | 50 | 52 | Output | Channel A differential output data D8 and D9 multiplexed |
DA10P | 53 | 55 | Output | Channel A differential output data D10 and D11 multiplexed |
DA10M | 52 | 54 | Output | Channel A differential output data D10 and D11 multiplexed |
DA12M | 54 | -- | Output | Channel A differential output data D12 and D13 multiplexed (ADS424x only) |
DA12P | 55 | -- | Output | Channel A differential output data D12 and D13 multiplexed (ADS424x only) |
DB0P | 61 | 63 | Output | Channel B differential output data pair, D0 and D1 multiplexed |
DB0M | 60 | 62 | Output | Channel B differential output data pair, D0 and D1 multiplexed |
DB2P | 63 | 3 | Output | Channel B differential output data D2 and D3 multiplexed |
DB2M | 62 | 2 | Output | Channel B differential output data D2 and D3 multiplexed |
DB4P | 3 | 5 | Output | Channel B differential output data D4 and D5 multiplexed |
DB4M | 2 | 4 | Output | Channel B differential output data D4 and D5 multiplexed |
DB6P | 5 | 7 | Output | Channel B differential output data D6 and D7 multiplexed |
DB6M | 4 | 6 | Output | Channel B differential output data D6 and D7 multiplexed |
DB8P | 7 | 9 | Output | Channel B differential output data D8 and D9 multiplexed |
DB8M | 6 | 8 | Output | Channel B differential output data D8 and D9 multiplexed |
DB10P | 9 | 11 | Output | Channel B differential output data D10 and D11 multiplexed |
DB10M | 8 | 10 | Output | Channel B differential output data D10 and D11 multiplexed |
DB12P | 11 | -- | Output | Channel B differential output data D12 and D13 multiplexed (ADS424x only) |
DB12M | 10 | -- | Output | Channel B differential output data D12 and D13 multiplexed (ADS424x only) |
DRGND | 49, PAD | 49, PAD | Input | Output buffer ground. The Thermal PAD is connected to DRGND |
DRVDD | 1, 48 | 1, 48 | Input | Output buffer supply |
INM_A | 30 | 30 | Input | Differential analog negative input, channel A |
INM_B | 20 | 20 | Input | Differential analog negative input, channel B |
INP_A | 29 | 29 | Input | Differential analog positive input, channel A |
INP_B | 19 | 19 | Input | Differential analog positive input, channel B |
NC | 38, 39, 58,
59 Refer to GUID-E7B6666C-5677-4A81-AC5E-9E605DDA532B.html#SBAS533GRAPH4838, GUID-E7B6666C-5677-4A81-AC5E-9E605DDA532B.html#SBAS533GRAPH8500, and GUID-E7B6666C-5677-4A81-AC5E-9E605DDA532B.html#SBAS533GRAPH1236 |
38, 39, 40, 41, 58, 59, 60, 61 | — | Do not connect, must be floated |
RESET | 12 | 12 | Input | Serial
interface RESET input. When using the serial interface mode, the internal registers must be initialized through a hardware RESET by applying a high pulse on this pin or by using the software reset option; refer to the Serial Interface Configuration section. In parallel interface mode, the RESET pin must be permanently tied high. SCLK and SEN are used as parallel control pins in this mode. This pin has an internal 150-kΩ pulldown resistor. |
SCLK | 13 | 13 | Input | This pin functions as a serial interface clock input when RESET is low. It controls the low-speed mode selection when RESET is tied high; see Table 8-6 for detailed information. This pin has an internal 150-kΩ pulldown resistor. |
SDATA | 14 | 14 | Input | Serial interface data input; this pin has an internal 150-kΩ pulldown resistor. |
SDOUT | 64 | 64 | Output | This pin functions as a serial interface register readout when the READOUT bit is enabled. When READOUT = 0, this pin is in high-impedance state. |
SEN | 15 | 15 | Input | This pin functions as a serial interface enable input when RESET is low. It controls the output interface and data format selection when RESET is tied high; see Table 8-7 for detailed information. This pin has an internal 150-kΩ pullup resistor to AVDD. |
VCM | 23 | 23 | Output | This pin outputs the common-mode voltage (0.95 V) that can be used externally to bias the analog input pins |