SBAS621B July   2013  – September 2015 ADS42JB46

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS42JB46
    6. 7.6  Electrical Characteristics: General
    7. 7.7  Timing Characteristics
    8. 7.8  Digital Characteristics
    9. 7.9  Reset Timing
    10. 7.10 Serial Interface Timing
    11. 7.11 Typical Characteristics: ADS42JB46
    12. 7.12 Typical Characteristics: Contour
      1. 7.12.1 Spurious-Free Dynamic Range (SFDR)
      2. 7.12.2 Signal-to-Noise Ratio (SNR)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital Gain
      2. 8.3.2 Overrange Indication
      3. 8.3.3 Input Clock Divider
      4. 8.3.4 Pin Controls
    4. 8.4 Device Functional Modes
      1. 8.4.1 JESD204B Interface
        1. 8.4.1.1 JESD204B Initial Lane Alignment (ILA)
        2. 8.4.1.2 JESD204B Test Patterns
        3. 8.4.1.3 JESD204B Frame Assembly
        4. 8.4.1.4 JESD Link Configuration
          1. 8.4.1.4.1 Configuration for 2-Lane (20x) SERDES Mode
          2. 8.4.1.4.2 Configuration for 4-Lane (10x) SERDES Mode
        5. 8.4.1.5 CML Outputs
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Register Initialization
        2. 8.5.1.2 Serial Register Write
        3. 8.5.1.3 Serial Register Readout
    6. 8.6 Register Maps
      1. 8.6.1 Summary of Serial Interface Registers
      2. 8.6.2 Description of Serial Interface Registers
        1. 8.6.2.1  Register Address 06
        2. 8.6.2.2  Register Address 07
        3. 8.6.2.3  Register Address 08
        4. 8.6.2.4  Register Address 0B
        5. 8.6.2.5  Register Address 0C
        6. 8.6.2.6  Register Address 0D
        7. 8.6.2.7  Register Address 0E
        8. 8.6.2.8  Register Address 0F
        9. 8.6.2.9  Register Address 10
        10. 8.6.2.10 Register Address 11
        11. 8.6.2.11 Register Address 12
        12. 8.6.2.12 Register Address 13
        13. 8.6.2.13 Register Address 1F
        14. 8.6.2.14 Register Address 26
        15. 8.6.2.15 Register Address 27
        16. 8.6.2.16 Register Address 2B
        17. 8.6.2.17 Register Address 2C
        18. 8.6.2.18 Register Address 2D
        19. 8.6.2.19 Register Address 30
        20. 8.6.2.20 Register Address 36
        21. 8.6.2.21 Register Address 37
        22. 8.6.2.22 Register Address 38
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Analog Input
          1. 9.2.2.1.1 Drive Circuit Requirements
          2. 9.2.2.1.2 Driving Circuit
        2. 9.2.2.2 Clock Input
        3. 9.2.2.3 SNR and Clock Jitter
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The ADS42JB46 is a highly linear, buffered analog input, dual-channel, analog-to-digital converter (ADC) with maximum sampling rate of 160 MSPS and JESD204B digital interface. The conversion process is initiated by a rising edge of the external input clock which samples the analog input signal. The sampled signal is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. At every clock edge, the sample propagates through the pipeline, resulting in a data latency of 23 clock cycles. The output is available in CML logic levels conforming to the JESD204B standard.

8.2 Functional Block Diagram

ADS42JB46 fbd_sbas621.gif

8.3 Feature Description

8.3.1 Digital Gain

The device includes gain settings that can be used to obtain improved SFDR performance (compared to no gain). Gain is programmable from –2 dB to 6 dB (in 0.5-dB steps). For each gain setting, the analog input full-scale range scales proportionally. Table 1 shows how full-scale input voltage changes when digital gains are programmed in 1-dB steps. Refer to Table 13 to set digital gain with a serial interface register.

SFDR improvement is achieved at the expense of SNR; for a 1-dB increase in digital gain, SNR degrades approximately between 0.5 dB and 1 dB. Therefore, gain can be used as a trade-off between SFDR and SNR. Note that the default gain after reset is 0 dB with a 2.0-VPP full-scale voltage.

Table 1. Full-Scale Range Across Gains

DIGITAL GAIN FULL-SCALE INPUT VOLTAGE
–2 dB 2.5 VPP(1)
–1 dB 2.2 VPP
0 dB (default) 2.0 VPP
1 dB 1.8 VPP
2 dB 1.6 VPP
3 dB 1.4 VPP
4 dB 1.25 VPP
5 dB 1.1 VPP
6 dB 1.0 VPP
(1) Shaded cells indicate performance settings used in the Electrical Characteristics and Typical Characteristics.

8.3.2 Overrange Indication

The device provides two different overrange indications. Normal OVR (default) is triggered if the final 16-bit data output exceeds the maximum code value. Fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and is presented after only nine clock cycles, thus enabling a quicker reaction to an overrange event. By default, the normal overrange indication is output on the OVRA and OVRB pins. Using the FAST OVR EN register bit, the fast OVR indication can be presented on the overrange pins instead.

The input voltage level at which the overload is detected is the threshold and is programmable using the FAST OVR THRESHOLD bits. FAST OVR is triggered nine output clock cycles after the overload condition occurs. The threshold voltage amplitude at which fast OVR is triggered is described in Equation 1:

Equation 1. 1 × [the decimal value of the FAST OVR THRESH bits] / 127

When digital is programmed (for gain values > 0 dB ), the threshold voltage amplitude is as given in Equation 2:

Equation 2. 10–Gain / 20 × [the decimal value of the FAST OVR THRESH bits] / 127

8.3.3 Input Clock Divider

The device is equipped with an internal divider on the clock input. By default, the clock divider is set to divide-by-1 operation. The divide-by-2 option supports a maximum 500-MHz input clock and the divide-by-4 option supports a maximum 1-GHz input clock frequency. A 320-MHz input clock with the divide-by-2 option and a 640-MHz input clock with the divide-by-4 option can be accepted because the maximum conversion rate of the device is 160 MSPS.

8.3.4 Pin Controls

The device power-down functions can be controlled either through the parallel control pins (STBY, PDN_GBL, CTRL1, and CTRL2) or through an SPI register setting. Table 2, Table 3, and Table 4 describe the parallel control pin functionality.

STBY places the device in a standby power-down mode. PDN_GBL places the device in global power-down mode.

Table 2. CTRL1, CTRL2 Pin Functions

CTRL1 CTRL2 DESCRIPTION
Low Low Normal operation
High Low Channel A powered down
Low High Channel B powered down
High High Global power-down

Table 3. PDN_GBL Pin Function

PDN_GBL DESCRIPTION
Low Normal operation
High Global power-down. Wake-up from this mode is slow.

Table 4. STBY Pin Function

STBY DESCRIPTION
Low Normal operation
High The ADCs are powered down while the input clock buffer and output CML buffers are alive. Wake-up from this mode is fast.

8.4 Device Functional Modes

8.4.1 JESD204B Interface

The JESD interface of the device, as shown in Figure 46 , supports device subclasses 0, 1, and 2 with a maximum output data rate (per lane) of 3.125 Gbps. An external SYSREF (subclass 1) or SYNC~ (subclass 2) signal is used to align all internal clock phases and the local multiframe clock to a specific sampling clock edge. This alignment allows synchronization of multiple devices in a system and minimizes timing and alignment uncertainty.

ADS42JB46 interface_las900.gifFigure 46. JESD204B Interface

Depending on the ADC sampling rate, the JESD204B output interface can be operated with either one or two lanes per ADC. The JESD204B interface can be configured with serial registers.

The JESD204B transmitter block (as shown in Figure 47) consists of the transport layer, data scrambler, and link layer. The transport layer maps the ADC output data into the selected JESD204B frame data format and determines whether the ADC output data or test patterns are transmitted. The link layer performs the 8b and 10b data encoding as well as the synchronization and initial lane alignment using the SYNC~ input signal. Optionally, data from the transport layer can be scrambled.

ADS42JB46 JESD204B_block_las900.gifFigure 47. JESD204B Block

8.4.1.1 JESD204B Initial Lane Alignment (ILA)

When receiving, the device asserts the SYNC~ signal (that is, a logic low signal is applied on SYNC~P and SYNC~M). The device then begins transmitting comma (K28.5) characters to establish the code group synchronization (CGS). When synchronization completes, the receiving device de-asserts the SYNC~ signal and the device begins the initial lane alignment (ILA) sequence with the next local multiframe clock boundary. The device transmits four multiframes, each containing K frames (where K is SPI programmable). Each multiframe contains the frame start and end symbols; the second multiframe also contains the JESD204 link configuration data.

8.4.1.2 JESD204B Test Patterns

There are three different test patterns available in the transport layer of the JESD204B interface. The device supports a clock output pattern, an encoded pattern, and a PRBS (215 – 1) pattern. These patterns can be enabled by a serial register write in register 26h, bits D[7:6].

8.4.1.3 JESD204B Frame Assembly

The JESD204B standard defines the following parameters:

  • L is the number of lanes per lane.
  • M is the number of converters per device.
  • F is the number of octets per frame clock period.
  • S is the number of samples per frame.

Table 5 lists the available JESD204B formats and valid device ranges. Ranges are limited by the maximum ADC sample frequency and the SERDES line rate.

Table 5. JESD240B Ranges

L M F S MAX ADC SAMPLING RATE (MSPS) MAX fSERDES (Gbps)
4 2 1 1 160 1.6
2 2 2 1 156.25 3.125

The detailed frame assembly in 10x and 20x modes for dual-channel operation is shown in Table 6. Note that unused lanes in 10x mode become 3-stated.

Table 6. Frame Assembly for Dual-Channel Mode(1)

LANE LMF = 421 LMF = 222
DA0 A0[15:8] A1[15:8] A2[15:8] A0[15:8] A0[7:0] A1[15:8] A1[7:0] A2[15:8] A2[7:0]
DA1 A0[7:0] A1[7:0] A2[7:0] — — — — — —
DB0 B0[15:8] B1[15:8] B2[15:8] B0[15:8] B0[7:0] B1[15:8] B1[7:0] B2[15:8] B2[7:0]
DB1 B0[7:0] B1[7:0] B2[7:0] — — — — — —
(1) Two LSBs of the 16-bit data are padded with '00' in the device.

Table 7. High-Frequency Modes Summary

REGISTER ADDRESS VALUE DESCRIPTION
Dh 90h High-frequency modes should be enabled for input frequencies greater than 250 MHz.
Eh 90h High-frequency modes should be enabled for input frequencies greater than 250 MHz.

8.4.1.4 JESD Link Configuration

During the lane alignment sequence, the device transmits JESD204B configuration parameters in the second multiframe of the ILA sequence. Configuration bits are mapped in octets, as per the JESD204B standard described in Figure 48 and Table 8.

ADS42JB46 Initial_lane_alignment_4_Multifrms.gifFigure 48. Initial Lane Alignment Sequence

Table 8. Mapping of Configuration Bits to Octets

OCTET NO MSB D6 D5 D4 D3 D2 D1 LSB
0 DID [7:0]
1 ADJCNT[3:0] BID[3:0]
2 X ADJDIR[0] PHADJ[0] LID[4:0]
3 SCR[0] L[4:0]
4 F[7:0]
5 K[4:0]
6 M[7:0]
7 CS[1:0] X N[4:0]
8 SUBCLASSV[2:0] N'[4:0]
9 JESDV[2:0] S[4:0]
10 HD[0] X X CF[4:0]
11 RES1[7:0]
12 RES2[7:0]
13 FCHK[7:0]

8.4.1.4.1 Configuration for 2-Lane (20x) SERDES Mode

Table 9 lists the values of the JESD204B configuration bits applicable for the 2-lane SERDES mode. The default value of these bits after reset is also specified in Table 9.

Table 9. Configuration for 2-Lane SERDES Mode

PARAMETER DESCRIPTION PARAMETER RANGE FIELD ENCODING DEFAULT VALUE AFTER RESET
ADJCNT Number of adjustment resolution steps to adjust the DAC LMFC. Applies to subclass 2 operation only. 0:15 ADJCNT[3:0] Binary value 0
ADJDIR Direction to adjust the DAC LMFC.
0 = Advance
1 = Delay applies to subclass 2 operation only		 0:1 ADJDIR[0] Binary value 0
BID Bank ID: extension to DID 0:15 BID[3:0] Binary value 0
CF Number of control words per frame clock period per link 0:32 CF[4:0] Binary value 0
CS Number of control bits per sample 0:3 CS[1:0] Binary value 0
DID Device (= link) identification number 0:255 DID[7:0] Binary value 0
F Number of octets per frame 1:256 F[7:0] Binary value minus 1 1
HD High-density format 0:1 HD[0] Binary value 0
JESDV JESD204 version
000 = JESD204A
001 = JESD204B 		0:7 JESDV[2:0] Binary value 1
K Number of frames per multiframe 1:32 K[4:0] Binary value minus 1 8
L Number of lanes per converter device (link) 1:32 L[4:0] Binary value minus 1 0
LID Lane identification number (within link) 0:31 LID[4:0] Binary value LID[0] = 0, LID[1] = 1
M Number of converters per device 1:256 M[7:0] Binary value minus 1 1
N Converter resolution 1:32 N[4:0] Binary value minus 1 15
N’ Total number of bits per sample 1:32 N'[4:0] Binary value minus 1 15
PHADJ Phase adjustment request to DAC subclass 2 only 0:1 PHADJ[0] Binary value 0
S Number of samples per converter per frame cycle 1:32 S[4:0] Binary value minus 1 0
SCR Scrambling enabled 0:1 SCR[0] Binary value 0
SUBCLASSV Device subclass version
000 = Subclass 0
001 = Subclass 1
010 = Subclass 2 		0:7 SUBCLASSV[2:0] Binary value 2
RES1 Device subclass version
000 = Subclass 0
001 = Subclass 1
010 = Subclass 2 		0:255 RES1[7:0] Binary value 0
RES2 Reserved field 2 0:255 RES2[7:0] Binary value 0
CHKSUM Checksum Σ (all above fields) mod 256 0:255 FCHK[7:0] Binary value 44, 45

8.4.1.4.2 Configuration for 4-Lane (10x) SERDES Mode

Table 10 lists the values of the JESD204 configuration bits applicable for the 4-lane SERDES mode. The default value of these bits after reset is also specified in Table 10.

Table 10. Configuration for 4-Lane SERDES Mode

PARAMETER DESCRIPTION PARAMETER RANGE FIELD ENCODING DEFAULT VALUE AFTER RESET
ADJCNT Number of adjustment resolution steps to adjust the DAC LMFC. Applies to subclass 2 operation only. 0:15 ADJCNT[3:0] Binary value 0
ADJDIR Direction to adjust the DAC LMFC.
0 = Advance
1 = Delay applies to subclass 2 operation only		 0:1 ADJDIR[0] Binary value 0
BID Bank ID: extension to DID 0:15 BID[3:0] Binary value 0
CF Number of control words per frame clock period per link 0:32 CF[4:0] Binary value 0
CS Number of control bits per sample 0:3 CS[1:0] Binary value 0
DID Device (= link) identification number 0:255 DID[7:0] Binary value 0
F Number of octets per frame 1:256 F[7:0] Binary value minus 1 0
HD High-density format 0:1 HD[0] Binary value 1
JESDV JESD204 version
000 = JESD204A
001 = JESD204B 		0:7 JESDV[2:0] Binary value 1
K Number of frames per multiframe 1:32 K[4:0] Binary value minus 1 16
L Number of lanes per converter device (link) 1:32 L[4:0] Binary value minus 1 3
LID Lane identification number (within link) 0:31 LID[4:0] Binary value LID[0] = 0, LID[1] = 1, LID[2] = 2, LID[3] = 3
M Number of converters per device 1:256 M[7:0] Binary value minus 1 1
N Converter resolution 1:32 N[4:0] Binary value minus 1 15
N’ Total number of bits per sample 1:32 N'[4:0] Binary value minus 1 15
PHADJ Phase adjustment request to DAC subclass 2 only 0:1 PHADJ[0] Binary value 0
S Number of samples per converter per frame cycle 1:32 S[4:0] Binary value minus 1 0
SCR Scrambling enabled 0:1 SCR[0] Binary value 0
SUBCLASSV Device subclass version
000 = Subclass 0
001 = Subclass 1
010 = Subclass 2 		0:7 SUBCLASSV[2:0] Binary value 2
RES1 Device subclass version
000 = Subclass 0
001 = Subclass 1
010 = Subclass 2 		0:255 RES1[7:0] Binary value 0
RES2 Reserved field 2 0:255 RES2[7:0] Binary value 0
CHKSUM Checksum Σ (all above fields) mod 256 0:255 FCHK[7:0] Binary value 54, 55, 56, 57

Table 11. Latency in Different Modes(1)(2)

MODE PARAMETER LATENCY (N Cycles) TYPICAL DATA DELAY (tD, ns)
10x ADC latency 23 0.65 × tS + 3
Normal OVR latency 14 6.7
Fast OVR latency 9 6.7
From SYNC~ falling edge to CGS phase(3) 16 0.65 × tS + 3
From SYNC~ rising edge to ILA sequence(4) 25 0.65 × tS + 3
20x ADC latency 22 0.85 × tS + 3
Normal OVR latency 14 6.7
Fast OVR latency 9 6.7
From SYNC~ falling edge to CGS phase(3) 15 0.85 × tS + 3
From SYNC~ rising edge to ILA sequence(4) 16 0.85 × tS + 3
(1) Overall latency = latency + tD.
(2) tS is the time period of the ADC conversion clock.
(3) Latency is specified for subclass 2. In subclass 0, the SYNC~ falling edge to CGS phase latency is 16 clock cycles in 10x mode and 15 clock cycles in 20x mode.
(4) Latency is specified for subclass 2. In subclass 0, the SYNC~ rising edge to ILA sequence latency is 11 clock cycles in 10x mode and 11 clock cycles in 20x mode.

8.4.1.5 CML Outputs

The device JESD204B transmitter uses differential CML output drivers. The CML output current is programmable from 5 mA to 20 mA using register settings.

The output driver includes an internal 50-Ω termination to the IOVDD supply. External 50-Ω termination resistors connected to the receiver common-mode voltage should be placed close to the receiver pins. AC-coupling can be used to avoid the common-mode mismatch between the transmitter and receiver, as shown in Figure 49.

ADS42JB46 Inputs_las900.gifFigure 49. CML Output Connections

Figure 50 shows the data eye measurements of the device JESD204B transmitter against the JESD204B transmitter mask at 3.125 Gbps (20x mode).

ADS42JB46 eye_3125gbps_las900.gifFigure 50. Eye Diagram: 3.125 Gbps

8.5 Programming

The ADS42JB46 can be configured using a serial programming interface, as described in the Serial Interface section. In addition, the device has four dedicated parallel pins (PDN_GBL, STBY, CTRL1, and CTRL2) for controlling the power-down modes.

8.5.1 Serial Interface

The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data output) pins. Serially shifting bits into the device is enabled when SEN is low. SDATA serial data are latched at every SCLK rising edge when SEN is active (low). Serial data are loaded into the register at every 16th SCLK rising edge when SEN is low. When the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The interface functions with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.

8.5.1.1 Register Initialization

After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin (of widths greater than 10 ns), as shown in Figure 2. During operation, the serial interface registers can be cleared (if required) either by:

  1. A hardware reset or
  2. By applying a software reset. When using the serial interface, set the RESET bit (register 08h, bit D0) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin remains low.

8.5.1.2 Serial Register Write

The internal device register can be programmed following these steps:

  1. Drive the SEN pin low.
  2. Set the R/W bit to ‘0’ (bit A7 of the 8-bit address).
  3. Set bit A6 in the address field to ‘0’.
  4. Initiate a serial interface cycle specifying the address of the register (A5 to A0) whose content must be written (as shown in Figure 1 and ).
  5. Write the 8-bit data that are latched on the SCLK rising edge.

8.5.1.3 Serial Register Readout

The device includes a mode where the contents of the internal registers can be read back. This readback mode may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC.

  1. Set the MSB of the 8-bit address A7 to '1'.
  2. Write the register address on bits A5 through A0 whose contents must be read. See Figure 51.
  3. The device outputs the contents (D[7:0]) of the selected register on the SDOUT pin (pin 45).
  4. The external controller can latch the contents at the SCLK rising edge.

When serial registers are enabled for writing (when bit A7 of the 8-bit address bus is '0'), the SDOUT pin is in a high-impedance mode. If serial readout is not used, the SDOUT pin must float. Figure 51 shows a timing diagram of this readout mode. SDOUT comes out at the SCLK falling edge with an approximate delay (tSD_DELAY) of 20 ns, as shown in Figure 52.

ADS42JB46 ser_read_las900.gifFigure 51. Serial Register Readout Timing Diagram
ADS42JB46 ai_tim_sdout_las900.gifFigure 52. SDOUT Timing Diagram

8.6 Register Maps

8.6.1 Summary of Serial Interface Registers

Table 12 lists the device registers.

Table 12. Register Map

REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
06 0 0 0 0 0 0 CLK DIV
07 0 0 0 0 0 SYSREF DELAY
08 PDN CHA PDN CHB STDBY DATA FORMAT Always write 1 0 0 RESET
0B CHA GAIN CHA GAIN EN 0 0
0C CHBGAIN CHB GAIN EN 0 0
0D HIGH FREQ 1 0 0 HIGH FREQ 1 0 0 0 FAST OVR EN
0E HIGH FREQ 2 0 0 HIGH FREQ 2 0 0 0 0
0F CHA TEST PATTERNS CHB TEST PATTERNS
10 CUSTOM PATTERN[15:8]
11 CUSTOM PATTERN[15:8]
12 CUSTOM PATTERN[15:8]
13 CUSTOM PATTERN[15:8]
1F Always write 0 FAST OVR THRESHOLD
26 SERDES TEST PATTERN IDLE SYNC TESTMODE EN FLIP ADC DATA LAN ALIGN FRAME ALIGN TX LINK CONFIG DATA0
27 0 0 0 0 0 0 CTRLK CTRLF
2B SCRAMBLE EN 0 0 0 0 0 0 0
2C 0 0 0 0 0 0 0 OCTETS PER FRAME
2D 0 0 0 FRAMES PER MULTIFRAME
30 SUBCLASS 0 0 0 0 0
36 SYNC REQ LMFC RESET MASK 0 0 OUTPUT CURRENT SEL
37 LINK LAYER TESTMODE LINK LAYER RPAT 0 PULSE DET MODES
38 FORCE LMFC COUNT LMFC COUNT INIT RELEASE ILANE SEQ

8.6.2 Description of Serial Interface Registers

8.6.2.1 Register Address 06

Figure 53. Register Address 06
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
06 0 0 0 0 0 0 CLK DIV
Default: 00h
D[1:0] CLK DIV Internal clock divider for input sample clock
00 Divide-by-1 (clock divider bypassed)
01 Divide-by-2
10 Divide-by-1
11 Divide-by-4

8.6.2.2 Register Address 07

Figure 54. Register Address 07
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
07 0 0 0 0 0 0 SYSREF DELAY
Default: 00h
D[2:0] SYSREF DELAY Controls the delay of the SYSREF input with respect to the input clock.
Typical values for the expected delay of different settings are:
000 0-ps delay
001 60-ps delay
010 120-ps delay
011 180-ps delay
100 240-ps delay
101 300-ps delay
110 360-ps delay
111 420-ps delay

8.6.2.3 Register Address 08

Figure 55. Register Address 08
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
08 PDN CHA PDN CHB STDBY DATA FORMAT Always write 1 0 0 RESET
Default: 00h
D7 PDN CHA Power-down channel A
0 Normal operation
1 Channel A power down
D6 PDN CHB Power-down channel B
0 Normal operation
1 Channel B power down
D5 STBY Dual ADC is placed into standby mode
0 Normal operation
1 Both ADCs are powered down (input clock buffer and CML output buffers are alive)
D4 DATA FORMAT Digital output data format
0 Twos complement
1 Offset binary
D3 Always write 1
Default value of this bit is '0'. This bit must always be set to '1'.
D0 RESET Software reset applied
This bit resets all internal registers to the default values and self-clears to ‘0’.

8.6.2.4 Register Address 0B

Figure 56. Register Address 0B
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
0B CHA GAIN CHA GAIN EN 0 0
Default: 00h
D[7:3] CHA GAIN Digital gain for channel A (must set the CHA GAIN EN bit first, bit D2)

Table 13. Digital Gain for Channel A

REGISTER VALUE DIGITAL GAIN FULL-SCALE INPUT VOLTAGE REGISTER VALUE DIGITAL GAIN FULL-SCALE INPUT VOLTAGE
00000 0 dB 2.0 VPP 01010 1.5 dB 1.7 VPP
00001 Do not use — 01011 2 dB 1.6 VPP
00010 Do not use — 01100 2.5 dB 1.5 VPP
00011 –2.0 dB 2.5 VPP 01101 3 dB 1.4 VPP
00100 –1.5 dB 2.4 VPP 01110 3.5 dB 1.3 VPP
00101 –1.0 dB 2.2 VPP 01111 4 dB 1.25 VPP
00110 –0.5 dB 2.1 VPP 10000 4.5 dB 1.2 VPP
00111 0 dB 2.0 VPP 10001 5 dB 1.1 VPP
01000 0.5 dB 1.9 VPP 10010 5.5 dB 1.05 VPP
01001 1 dB 1.8 VPP 10011 6 dB 1.0 VPP
D2 CHA GAIN EN Digital gain enable bit for channel A
0 Digital gain disabled
1 Digital gain enabled

8.6.2.5 Register Address 0C

Figure 57. Register Address 0C
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
0C CHB GAIN CHB GAIN EN 0 0
Default: 00h
D[7:3] CHB GAIN Digital gain for channel B (must set the CHA GAIN EN bit first, bit D2)

Table 14. Digital Gain for Channel B

REGISTER VALUE DIGITAL GAIN FULL-SCALE INPUT VOLTAGE REGISTER VALUE DIGITAL GAIN FULL-SCALE INPUT VOLTAGE
00000 0 dB 2.0 VPP 01010 1.5 dB 1.7 VPP
00001 Do not use — 01011 2 dB 1.6 VPP
00010 Do not use — 01100 2.5 dB 1.5 VPP
00011 –2.0 dB 2.5 VPP 01101 3 dB 1.4 VPP
00100 –1.5 dB 2.4 VPP 01110 3.5 dB 1.3 VPP
00101 –1.0 dB 2.2 VPP 01111 4 dB 1.25 VPP
00110 –0.5 dB 2.1 VPP 10000 4.5 dB 1.2 VPP
00111 0 dB 2.0 VPP 10001 5 dB 1.1 VPP
01000 0.5 dB 1.9 VPP 10010 5.5 dB 1.05 VPP
01001 1 dB 1.8 VPP 10011 6 dB 1.0 VPP
D2 CHB GAIN EN Digital gain enable bit for channel B
0 Digital gain disabled
1 Digital gain enabled

8.6.2.6 Register Address 0D

Figure 58. Register Address 0D
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
0D HIGH FREQ 1 0 0 HIGH FREQ 1 0 0 0 FAST OVR EN
D7, D4 HIGH FREQ 1 High-frequency mode 1
00 Default
11 Use for input frequencies > 250 MHz along with HIGH FREQ 2
D0 FAST OVR EN Selects if normal or fast OVR signal is presented on OVRA, OVRB pins
0 Normal OVR on OVRA, OVRB pins
1 Fast OVR on OVRA, OVRB pins

8.6.2.7 Register Address 0E

Figure 59. Register Address 0E
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
0E HIGH FREQ 2 0 0 HIGH FREQ 2 0 0 0 0
D7, D4 HIGH FREQ 2 High-frequency mode 2
00 Default
11 Use for input frequencies > 250 MHz along with HIGH FREQ 1

8.6.2.8 Register Address 0F

Figure 60. Register Address 0F
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
0F CHA TEST PATTERNS CHB TEST PATTERNS
Default: 00h
D[7:4] CHA TEST PATTERNS Channel A test pattern programmability
The 16-bit test pattern data are selected as the input to the JESD block (the last two LSBs of the 16-bit data are replaced by '00').
0000 Normal operation
0001 All '0's
0010 All '1's
0011 Toggle pattern: Data alternate between 10101010101010 and 01010101010101.
0100 Digital ramp: Data increment by 1 LSB every fourth clock cycle from code 0 to 16383.
0101 Do not use
0110 Single pattern: Data are the same as that programmed by the CUSTOM PATTERN 1[15:2] register bits.
0111 Double pattern: Data alternate between CUSTOM PATTERN 1[15:2] and CUSTOM PATTERN 2[15:2].
1000 Deskew pattern: Data are AAA8h.
1001 Do not use
1010 PRBS pattern: Data are a sequence of pseudo random numbers.
1011 8-point sine wave: Data are a repetitive sequence of the following eight numbers, forming a sine-wave in twos complement format:
0, 2399, 8192, 13984, 16383, 13984, 8192, 2399.
D3-D0 CHB TEST PATTERNS Channel B test pattern programmability
The 16-bit test pattern data are selected as the input to the JESD block (the last two LSBs of the 16-bit data are replaced by '00').
0000 Normal operation
0001 All '0's
0010 All '1's
0011 Toggle pattern: Data alternate between 10101010101010 and 01010101010101.
0100 Digital ramp: Data increment by 1 LSB every fourth clock cycle from code 0 to 16383.
0101 Do not use
0110 Single pattern: Data are the same as that programmed by the CUSTOM PATTERN 1[15:2] register bits.
0111 Double pattern: Data alternate between CUSTOM PATTERN 1[15:2] and CUSTOM PATTERN 2[15:2].
1000 Deskew pattern: Data are AAA8h.
1001 Do not use
1010 PRBS pattern: Data are a sequence of pseudo random numbers.
1011 8-point sine wave: Data are a repetitive sequence of the following eight numbers, forming a sine-wave in twos complement format:
0, 2399, 8192, 13984, 16383, 13984, 8192, 2399.

8.6.2.9 Register Address 10

Figure 61. Register Address 10
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
10 CUSTOM PATTERN 1[15:8]
Default: 00h
D[7:0] CUSTOM PATTERN 1[15:8] These bits set the custom pattern 1[15:8] for both channels.

8.6.2.10 Register Address 11

Figure 62. Register Address 11
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
11 CUSTOM PATTERN 1[7:0]
Default: 00h
D[7:0] CUSTOM PATTERN 1[7:0] These bits set the custom pattern 1[7:0] for both channels.

8.6.2.11 Register Address 12

Figure 63. Register Address 12
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
12 CUSTOM PATTERN 2[15:8]
Default: 00h
D[7:0] CUSTOM PATTERN 2[15:8] These bits set the custom pattern 2[15:8] for both channels.

8.6.2.12 Register Address 13

Figure 64. Register Address 13
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
13 CUSTOM PATTERN 2[7:0]
Default: 00h
D[7:0] CUSTOM PATTERN 2[7:0] These bits set the custom pattern 2[7:0] for both channels.

8.6.2.13 Register Address 1F

Figure 65. Register Address 1F
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
1F Always write 0 FAST OVR THRESHOLD
Default: FFh
D7 Always write 0
Default value of this bit is '1'. Always write this bit to '0' when the fast OVR thresholds are programmed.
D[6:0] FAST OVR THRESHOLD
The device has a fast OVR mode that indicates an overload condition at the ADC input. The input voltage level at which the overload is detected is referred to as the threshold and is programmable using the FAST OVR THRESHOLD bits. FAST OVR is triggered nine output clock cycles after the overload condition occurs. The threshold at which fast OVR is triggered is (full-scale × [the decimal value of the FAST OVR THRESHOLD bits] / 127). See the Overrange Indication section for details.

8.6.2.14 Register Address 26

Figure 66. Register Address 26
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
26 SERDES TEST PATTERN IDLE SYNC TESTMODE EN FLIP ADC DATA LANE ALIGN FRANE ALIGN TX LINK CONFIG DATA
Default: 00h
D[7:6] SERDES TEST PATTERN Sets test patterns in the transport layer of the JESD204B interface.
00 Normal operation
01 Outputs clock pattern: Output is in a 10101010 pattern
10 Encoded pattern: Output is 1111111100000000
11 PRBS sequence: Output is 215 – 1
D5 IDLE SYNC Sets the output pattern when SYNC~ is asserted.
0 Sync code is k28.5 (0xBCBC)
1 Sync code is 0xBC50
D4 TESTMODE EN Generates a long transport layer test pattern mode according to clause 5.1.63 of the JESD204B specification.
0 Test mode disabled
1 Test mode enabled
D3 FLIP ADC DATA
0 Normal operation
1 Output data order is reversed: MSB – LSB
D2 LANE ALIGN Inserts a lane alignment character (K28.3) for the receiver to align to the lane boundary, as per section 5.3.3.5 of the JESD204B specification.
0 Lane alignment characters are not inserted.
1 Inserts lane alignment characters
D1 FRAME ALIGN Inserts a frame alignment character (K28.7) for the receiver to align to the frame boundary, as per section 5.3.3.4 of the JESD204B specification.
0 Frame alignment characters are not inserted.
1 Inserts frame alignment characters
D0 TX LINK CONFIG DATA Disables sending the initial link alignment (ILA) sequence when SYNC~ is de-asserted, '0'.
0 ILA enabled
1 ILA disabled

8.6.2.15 Register Address 27

Figure 67. Register Address 27
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
27 0 0 0 0 0 0 CTRL K CTRL F
Default: 00h
D1 CTRL K Enables bit for number of frames per multiframe.
0 Default
1 Frames per multiframe can be set in register 2Dh
D0 CTRL F Enables bit for number of octets per frame.
0 Default
1 Octets per frame can be specified in register 2Ch

8.6.2.16 Register Address 2B

Figure 68. Register Address 2B
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
2B SCRAMBLE EN 0 0 0 0 0 0 0
Default: 00h
D7 SCRAMBLE EN Scramble enable bit in the JESD204B interface
0 Scrambling disabled
1 Scrambling enabled

8.6.2.17 Register Address 2C

Figure 69. Register Address 2C
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
2C 0 0 0 0 0 0 0 OCTETS PER FRAME
Default: 00h
D[7:0] OCTETS PER FRAME Sets number of octets per frame (F).
0 10x mode using two lanes per ADC
1 20x mode using one lane per ADC

8.6.2.18 Register Address 2D

Figure 70. Register Address 2D
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
2D 0 0 0 FRAMES PER MULTIFRAME
Default: 00h
D[4:0] FRAMES PER MULTIFRAME Sets number of frames per multiframe.
After reset, the default settings for frames per multiframe are:
10x K = 16
20x K = 8
For each mode, K should not be set to a lower value.

8.6.2.19 Register Address 30

Figure 71. Register Address 30
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
30 SUBCLASS 0 0 0 0 0
Default: 40h
D[7:5] SUBCLASS Sets JESD204B subclass. Note that the default value of these bits after reset is '010', which makes subclass 2 the default class.
000 Subclass 0 Backward compatibility with JESD204A
001 Subclass 1 Deterministic latency using the SYSREF signal
010 Subclass 2 Deterministic latency using SYNC~ detection (default subclass after reset)

8.6.2.20 Register Address 36

Figure 72. Register Address 36
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
36 SYNC REQ LMFC RESET MASK 0 0 OUTPUT CURRENT SEL
Default: 00h
D7 SYNC REQ Generates a synchronization request.
0 Normal operation
1 Generates sync request
D6 LMFC RESET MASK Mask the LMFC reset coming to digital.
0 LMFC reset is not masked
1 Ignores LMFC reset
D3-D0 OUTPUT CURRENT SEL Changes the JESD output buffer current.
0000 16 mA 1000 8 mA
0001 15 mA 1001 7 mA
0010 14 mA 1010 6 mA
0011 13 mA 1011 5 mA
0100 20 mA 1100 12 mA
0101 19 mA 1101 11 mA
0110 18 mA 1110 10 mA
0111 17 mA 1111 9 mA

8.6.2.21 Register Address 37

Figure 73. Register Address 37
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
37 LINK LAYER TESTMODE LINK LAYER RPAT 0 PULSE DET MODES
Default: 00h
D[7:5] LINK LAYER TESTMODE Generates a pattern according to clause 5.3.3.8.2 of the JESD204B document.
000 Normal ADC data
001 D21.5 (high-frequency jitter pattern)
010 K28.5 (mixed-frequency jitter pattern)
011 Repeats initial lane alignment (generates a K28.5 character and continuously repeats the lane alignment sequences)
100 12-octet RPAT jitter pattern
D4 LINK LAYER RPAT Changes the running disparity in the modified RPAT pattern test mode (only when the link layer test mode = 100).
0 Normal operation
1 Changes disparity
D[2:0] PULSE DET MODES Selects different detection modes for SYSREF (subclass 1) and SYNC (subclass 2).
D2 D1 D0 FUNCTIONALITY
0 Don’t care 0 Allows all pulses to reset input clock dividers
1 Don’t care 0 Do not allow reset of analog clock dividers
Don’t care 0 -> 1 transition 1 Allows one pulse immediately after the 0 -> 1 transition to reset the divider

8.6.2.22 Register Address 38

Figure 74. Register Address 38
REGISTER ADDRESS REGISTER DATA
A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
38 FORCE LMFC COUNT LMFC COUNT INIT RELEASE ILANE SEQ
Default: 00h
D7 FORCE LMFC COUNT Forces an LMFC count.
0 Normal operation
1 Enables using a different starting value for the LMFC counter
D[6:2] LMFC COUNT INIT SYSREF receives the digital block and resets the LMFC count to '0'.
K28.5 stops transmitting when the LMFC count reaches 31. The initial value that the LMFC count resets to can be set using LMFC COUNT INIT. In this manner, the Rx can be synchronized early because the Rx gets the LANE ALIGNMENT SEQUENCE early. The FORCE LMFC COUNT register bit must be enabled.
D[1:0] RELEASE ILANE SEQ Delays the generation of the lane alignment sequence by 0, 1, 2, or 3 multiframes after the code group synchronization.
00 0
01 1
10 2
11 3