SBAS603B April 2013 – November 2020 ADS4449
PRODUCTION DATA
The ADS4449 belong to TI’s low-power family of quad-channel, 14-bit, analog-to-digital converters (ADCs). High performance is maintained while power is reduced for power-sensitive applications. In addition to its low power and high performance, the ADS4449 has a number of digital features and operating modes to enable design flexibility.
At every falling edge of the input clock, the analog input signal for each channel is sampled simultaneously. The sampled signal in each channel is converted by a pipeline of low-resolution stages. In each stage, the sampled-and-held signal is converted by a high-speed, low-resolution, flash sub-ADC. The difference (residue) between the stage input and quantized equivalent is gained and propagates to the next stage. At every clock, each subsequent stage resolves the sampled input with greater accuracy. The digital outputs from all stages are combined in a digital correction logic block and are digitally processed to create the final code, after a data latency of 10 clock cycles. The digital output is available in a double data rate (DDR) low-voltage differential signaling (LVDS) interface and is coded in binary twos complement format.
The ADS4449 can be configured with a serial programming interface (SPI), as described in the Section 8.5.1 section. In addition, the device has control terminals that control power-down.