SBAS603 Data sheet

SBAS603B April 2013 – November 2020 ADS4449

PRODUCTION DATA

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ZCR|144
- MPBGA77A

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6.7 Timing Requirements

Typical values are at 25°C, AVDD33 = 3.3 V, AVDD = 1.9 V, DRVDD = 1.8 V, sine-wave input clock, C_LOAD = 3.3 pF⁽²⁾, and R_LOAD = 100 Ω⁽³⁾, unless otherwise noted.
Minimum and maximum values are across the full temperature range of T_MIN = –40°C to T_MAX = 85°C.

See Note ⁽¹⁾			MIN	NOM	MAX	UNIT
t_A	Aperture delay		0.7	1.2	1.6	ns
	Aperture delay matching	Between any two channels of the same device		±70		ps
	Variation of aperture delay	Between two devices at the same temperature and DRVDD supply		±150		ps
t_J	Aperture jitter			140		fs rms
	Wake up time	Time to valid data after coming out of global power down		100		µs
	Wake up time	Time to valid data after coming out of channel power down		10		µs
	ADC latency⁽⁴⁾⁽⁵⁾	Default latency in 14-bit mode		10		Output clock cycles
		Digital gain enabled		13
		Digital gain and offset correction enabled		14
OUTPUT TIMING⁽⁶⁾
t_SU	Data setup time⁽⁷⁾⁽⁸⁾⁽⁹⁾	Data valid to CLKOUTxxP zero-crossing	0.6	0.85		ns
t_H	Data hold time⁽⁷⁾⁽⁸⁾⁽⁹⁾	CLKOUTxxP zero-crossing to data becoming invalid	0.6	0.84		ns
	LVDS bit clock duty cycle	Differential clock duty cycle (CLKOUTxxP – CLKOUTxxM)		50%
t_PDI	Clock propagation delay⁽⁵⁾	Input clock falling edge cross-over to output clock falling edge cross-over, 184 MSPS ≤ sampling frequency ≤ 250 MSPS	0.25 × t_S + t_delay			ns
t_delay	Delay time	Input clock falling edge cross-over to output clock falling edge cross-over, 184 MSPS ≤ sampling frequency ≤ 250 MSPS	6.9	8.65	10.5	ns
t_RISE, t_FALL	Data rise and fall time	Rise time measured from –100 mV to 100 mV		0.1		ns
t_CLKRISE, t_CLKFALL	Output clock rise and fall time	Rise time measured from –100 mV to 100 mV		0.1		ns

(1) Timing parameters are ensured by design and characterization and are not tested in production.

(2) C_LOAD is the effective external single-ended load capacitance between each output terminal and ground.

(3) R_LOAD is the differential load resistance between the LVDS output pair.

(4) ADC latency is given for channels B and D. For channels A and C, latency reduces by half of the output clock cycles.

(5) Overall latency = ADC latency + t_PDI.

(6) Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and load. Setup and hold time specifications take into account the effect of jitter on the output data and clock.

(7) Data valid refers to a logic high of 100 mV and a logic low of –100 mV.

(8) Note that these numbers are taken with delayed output clocks by writing the following registers: address A9h, value 02h; and address ACh, value 60h. Refer to the section. By default after reset, minimum setup time and minimum hold times are 520 ps each.

(9) The setup and hold times of a channel are measured with respect to the same channel output clock.