SBAS603B April 2013 – November 2020 ADS4449
PRODUCTION DATA
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
SUPPLIES | ||||||
AVDD33 | Supply voltage | 3.15 | 3.3 | 3.45 | V | |
AVDD | 1.8 | 1.9 | 2 | V | ||
DRVDD | 1.7 | 1.8 | 2 | V | ||
ANALOG INPUTS | ||||||
Differential input voltage range | 2 | VPP | ||||
VIC | Input common-mode voltage | VCM ± 0.025 | V | |||
Analog input common-mode current (per input terminal of each channel) | 1.5 | µA/MSPS | ||||
VCM current capability | 5 | mA | ||||
Maximum analog input frequency | 2-VPP input amplitude(2) | 400 | MHz | |||
1.4-VPP input amplitude | 500 | |||||
CLOCK INPUTS | ||||||
Input clock sample rate (1) | 10 | 250 | MSPS | |||
Input clock amplitude differential (VCLKP – VCLKM) | Sine wave, ac-coupled | 0.2 | 1.5 | VPP | ||
LVPECL, ac-coupled | 1.6 | |||||
LVDS, ac-coupled | 0.7 | |||||
LVCMOS, single-ended, ac-coupled | 1.8 | |||||
Input clock duty cycle | 40% | 50% | 60% | |||
DIGITAL OUTPUTS | ||||||
CLOAD | Maximum external load capacitance from each output terminal to DRVSS (default strength) | 3.3 | pF | |||
RLOAD | Differential load resistance between the LVDS output pairs (LVDS mode) | 100 | Ω | |||
TEMPERATURE RANGE | ||||||
TA | Operating free-air temperature | –40 | 85 | °C | ||
TJ | Operating junction temperature | Recommended | 105 | °C | ||
Maximum rated (2) | 125 |