SBAS603B April   2013  – November 2020 ADS4449

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Digital Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Timing Characteristics, Serial interface
    9. 6.9  Typical Characteristics
    10. 6.10 Typical Characteristics: Contour
  7. 7 Parameter Measurement Information
    1. 7.1 LVDS Output Timing
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Overrange Indication (OVRxx)
      2. 8.3.2 Gain for SFDR and SNR Trade-Off
    4. 8.4 Device Functional Modes
      1. 8.4.1 Special Performance Modes
      2. 8.4.2 Digital Output Information
        1. 8.4.2.1 DDR LVDS Outputs
          1. 8.4.2.1.1 LVDS Output Data and Clock Buffers
          2. 8.4.2.1.2 Output Data Format
      3. 8.4.3 Using High SNR Mode Register Settings
      4. 8.4.4 Input Common Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Register Initialization
        2. 8.5.1.2 Serial Register Readout
    6. 8.6 Register Maps
      1. 8.6.1 Register Description
        1. 8.6.1.1  Register Address 00h (Default = 00h)
        2. 8.6.1.2  Register Address 01h (Default = 00h)
        3. 8.6.1.3  Register Address 25h (Default = 00h)
        4. 8.6.1.4  Register Address 2bh (Default = 00h)
        5. 8.6.1.5  Register Address 31h (Default = 00h)
        6. 8.6.1.6  Register Address 37h (Default = 00h)
        7. 8.6.1.7  Register Address 3dh (Default = 00h)
        8. 8.6.1.8  Register Address 3fh (Default = 00h)
        9. 8.6.1.9  Register Address 40h (Default = 00h)
        10. 8.6.1.10 Register Address 42h (Default = 00h)
        11. 8.6.1.11 Register Address 45h (Default = 00h)
        12. 8.6.1.12 Register Address 4ah (Defalut = 00h)
        13. 8.6.1.13 Register Address 62h (Default = 00h)
        14. 8.6.1.14 Register Address 7ah (Default = 00h)
        15. 8.6.1.15 Register Address 92h (Default = 00h)
        16. 8.6.1.16 Register Address A9h (Default = 00h)
        17. 8.6.1.17 Register Address Ach (Default = 00h)
        18. 8.6.1.18 Register Address C3h (Default = 00h)
        19. 8.6.1.19 Register Address C4h (Default = 00h)
        20. 8.6.1.20 Register Address Cfh (Default = 00h)
        21. 8.6.1.21 Register Address D6h (Default = 00h)
        22. 8.6.1.22 Register Address D7h (Default = 00h)
        23. 8.6.1.23 Register Address F1h (Default = 00h)
        24. 8.6.1.24 Register Address 58h (Default = 00h)
        25. 8.6.1.25 Register Address 59h (Default = 00h)
        26. 8.6.1.26 Register Address 70h (Default = 00h)
        27. 8.6.1.27 Register Address 71h (Default = 00h)
        28. 8.6.1.28 Register Address 88h (Default = 00h)
        29. 8.6.1.29 Register Address 89h (Default = 00h)
        30. 8.6.1.30 Register Address A0h (Default = 00h)
        31. 8.6.1.31 Register Address A1h (Default = 00h)
        32. 8.6.1.32 Register Address Feh (Default = 00h)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
      4. 9.2.4 Enabling 14-Bit Resolution
      5. 9.2.5 Analog Input
      6. 9.2.6 Drive Circuit Requirements
      7. 9.2.7 Clock Input
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8.4.2.1.1 LVDS Output Data and Clock Buffers

The equivalent circuit of each LVDS output buffer is shown in Figure 8-5. After reset, the buffer presents an output impedance of 100 Ω to match with the external 100-Ω termination.

The VDIFF voltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100-Ω external termination. The VDIFF voltage is programmable using the LVDS SWING register bits (refer to Table 8-3, register address 01h). The buffer output impedance behaves similar to a source-side series termination. By absorbing reflections from the receiver end, the source-side termination helps improve signal integrity.

GUID-B9CDA285-EB14-4D4E-83DD-DCA6C474C670-low.gifFigure 8-5 LVDS Buffer Equivalent Circuit