SBAS603 Data sheet

SBAS603B April 2013 – November 2020 ADS4449

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

ZCR|144
- MPBGA77A

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6.6 Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD33 = 3.3 V, AVDD = 1.9 V, and DRVDD = 1.8 V, unless otherwise noted.

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
DIGITAL INPUTS⁽¹⁾ (RESET, SCLK, SDATA, SEN, PDN)
V_IH	High-level input voltage		All digital inputs support 1.8-V logic levels. SPI supports 3.3-V logic levels.	1.25			V
V_IL	Low-level input voltage		All digital inputs support 1.8-V logic levels. SPI supports 3.3-V logic levels.			0.45	V
I_IH	High-level input current	RESET, SCLK, PDN terminals	V_HIGH = 1.8 V		10		µA
I_IH	High-level input current	SEN⁽²⁾ terminal	V_HIGH = 1.8 V		0		µA
I_IL	Low-level input current	RESET, SCLK, PDN terminals	V_LOW = 0 V		0		µA
I_IL	Low-level input current	SEN terminal	V_LOW = 0 V		10		µA
DIGITAL OUTPUTS (SDOUT)
V_OH	High-level output voltage			DRVDD – 0.1	DRVDD		V
V_OL	Low-level output voltage				0	0.1	V
DIGITAL OUTPUTS, LVDS INTERFACE (DAB[13:0]P, DAB[13:0]M, DCD[13:0]P, DCD[13:0]M, CLKOUTABP, CLKOUTABM, CLKOUTCDP, CLKOUTCDM)
V_ODH	High-level output differential voltage⁽³⁾		Standard-swing LVDS	270	350	465	mV
V_ODL	Low-level output differential		Standard-swing LVDS	–465	–350	–270	mV
V_OCM	Output common-mode voltage				1.05		V

(1) RESET, SDATA, and SCLK have an internal 150-kΩ pull-down resistor.

(2) SEN has an internal 150-kΩ pull-up resistor to DRVDD.

(3) with an external 100-Ω termination.