This configuration improves the common-mode noise immunity and even-order harmonic rejection. A 5-Ω to 15-Ω resistor in series with each input terminal is recommended to damp out ringing caused by package parasitics.

Glitches are caused by opening and closing the sampling switches. The driving circuit should present a low source impedance to absorb these glitches, otherwise these glitches may limit performance. A low impedance path between the analog input terminals and VCM is required from the common-mode switching currents perspective as well. This impedance can be achieved by using two resistors from each input terminated to the common-mode voltage (VCM).

The device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the sampling glitches inside the device itself. The R-C component values are also optimized to support high input bandwidth (up to 500 MHz). However, using an external R-LC-R filter (refer to Figure 9-4, Figure 9-5, Figure 9-6, Figure 9-7, and Figure 9-10) improves glitch filtering, thus further resulting in better performance.

In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched source impedance. In doing so, the ADC input impedance must be considered. Figure 9-1, Figure 9-2, and Figure 9-3 show the impedance (Z_IN = R_IN || C_IN) at the ADC input terminals.

Spurious-free dynamic range (SFDR) performance can be limited because of several reasons (such as the effect of sampling glitches, sampling circuit nonlinearity, and quantizer nonlinearity that follows the sampling circuit). Depending on the input frequency, sampling rate, and input amplitude, one of these metrics plays a dominant part in limiting performance. At very high input frequencies, SFDR is determined largely by the device sampling circuit nonlinearity. At low input amplitudes, the quantizer nonlinearity typically limits performance.