SLAS760D May   2011  – November 2015 ADS5263

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics, Dynamic Performance - 16-Bit ADC
    6. 7.6  Electrical Characteristics, General - 16-Bit ADC Mode
    7. 7.7  Electrical Characteristics, Dynamic Performance - 14-Bit ADC
    8. 7.8  Digital Characteristics
    9. 7.9  Timing Requirements
    10. 7.10 LVDS Timing at Lower Sampling Frequencies - 2 Wire, 8× Serialization
    11. 7.11 LVDS Timing for 1 Wire 16× Serialization
    12. 7.12 LVDS Timing for 2 Wire, 7× Serialization
    13. 7.13 LVDS Timing for 1 Wire, 14× Serialization
    14. 7.14 Serial Interface Timing Requirements
    15. 7.15 Reset Switching Characteristics
    16. 7.16 Typical Characteristics
      1. 7.16.1 Typical Characteristic - 16-Bit ADC Mode
      2. 7.16.2 Typical Characteristic - 14-Bit ADC Mode
      3. 7.16.3 Typical Characteristics - Common Plots
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital Processing Blocks
      2. 8.3.2 Digital Gain
      3. 8.3.3 Digital Filter
      4. 8.3.4 Custom Filter Coefficients
        1. 8.3.4.1 Custom Filter Without Decimation
      5. 8.3.5 Digital Averaging
      6. 8.3.6 Performance with Digital Processing Blocks
        1. 8.3.6.1 18-Bit Data Output with Digital Processing
      7. 8.3.7 Flexible Mapping o Channel Data to LVDS Outputs
      8. 8.3.8 Output LVDS Interface
      9. 8.3.9 Programmable LCLK Phase
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration
      2. 8.4.2 Serial Register Readout
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
      2. 8.5.2 Register Initialization
    6. 8.6 Register Maps
      1. 8.6.1 Default State After Reset
      2. 8.6.2 Description of Serial Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Analog Input
        1. 9.1.1.1 Drive Circuit Requirements
      2. 9.1.2 Large and Small Signal Input Bandwidth
      3. 9.1.3 Clamp Function For CCD Signals
        1. 9.1.3.1 Differential Input Drive
        2. 9.1.3.2 Clamp Operation
        3. 9.1.3.3 Synchronization to External CCD Timing
      4. 9.1.4 Low-Frequency Noise Suppression
      5. 9.1.5 External Reference Mode
    2. 9.2 Typical Applications
      1. 9.2.1 Driving Circuit Design: Low Input Frequencies (< 50 MHz)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Driving Circuit Design: Input Frequencies > 50 MHz
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Definition of Specifications
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging
      1. 13.1.1 Exposed Pad
      2. 13.1.2 Non-Magnetic Package

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

QFN Package
64-Pin With Thermal Pad
Top View
ADS5263 P0056-19_LAS760.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
ADCLKM 24 O LVDS frame clock (1X) – negative output
ADCLKP 23 O LVDS frame clock (1X) – positive output
AGND 3, 6, 9, 37,
40, 43, 46		 I Analog ground
AVDD 50, 57, 60 I Analog power supply, 3.3 V
CLKM 59 I Negative differential clock input. For single-ended clock, tie CLKM to ground.
CLKP 58 I Positive differential clock input
CS 61 I Serial interface enable input, active LOW. The pin has an internal 300-kΩ pulldown resistor to ground
IN1A_P, IN1A_M 1, 2 I Differential analog input for channel 1, 16 bit ADC
IN1B_P, IN1B_M 4, 5 I Differential analog input for channel 1, 14 bit ADC
IN2A_P, IN2A_M 7, 8 I Differential analog input for channel 2, 16 bit ADC
IN2B_P, IN2B_M 10, 11 I Differential analog input for channel 2, 14 bit ADC
IN3A_P, IN3A_M 41, 42 I Differential analog input for channel 3, 16 bit ADC
IN3B_P, IN3B_M 38, 39 I Differential analog input for channel 3, 14 bit ADC
IN4A_P, IN4A_M 47, 48 I Differential analog input for channel 4, 16 bit ADC
IN4B_P, IN4B_M 44, 45 I Differential analog input for channel 4, 14 bit ADC
INT/EXT 56 I Internal/external reference mode select input
Logic HIGH –internal reference
Logic LOW – external reference
ISET 51 I Bias pin – 56.2 kΩ resistor (1% tolerance value) to ground
LCLKM 26 O LVDS bit clock (8X) – negative output
LCLKP 25 O LVDS bit clock (8X) – positive output
LGND 12, 14, 36 I Digital ground
LVDD 35 I Digital and I/O power supply, 1.8 V
OUT1P, OUT1M 15, 16 O Wire 1, channel 1 LVDS differential output
OUT2P, OUT2M 17, 18 O Wire 2, channel 1 LVDS differential output
OUT3P, OUT3M 19, 20 O Wire 1, channel 2, LVDS differential output
OUT4P, OUT4M 21, 22 O Wire 2, channel 2 LVDS differential output
OUT5P, OUT5M 27, 28 O Wire 1, channel 3 LVDS differential output
OUT6P, OUT6M 29, 30 O Wire 2, channel 3 LVDS differential output
OUT7P, OUT7M 31, 32 O Wire 1, channel 4 LVDS differential output
OUT8P, OUT8M 33, 34 O Wire 2, channel 4 LVDS differential output
PD 13 I Power-down input
NC 54, 55 Do not connect
RESET 64 I Serial interface RESET input, active LOW.
When using the serial interface mode, the user must initialize internal registers through hardware RESET by applying a low-going pulse on this pin or by using software reset option. See the Serial Interface section.
SCLK 63 I Serial interface clock input. The pin has an internal 300-kΩ pulldown resistor.
SDATA 62 I Serial interface data input. The pin has an internal 300-kΩ pulldown resistor.
SDOUT 52 O Serial register readout
This pin is in the high-impedance state after reset. When the <READOUT> bit is set, the SDOUT pin becomes active. This is a CMOS digital output running from the AVDD supply.
SYNC 49 I Input signal to synchronize channels and chips when used with reduced output data rates
Alternate function: Clamp signal input (14-bit ADC mode only)
VCM 53 IO Internal reference mode: Outputs the common-mode voltage (1.5 V) that can be used externally to bias the analog input.
External reference mode: Apply voltage input that sets the reference for ADC operation.